Type conversion problem

Hi,

I am having trouble with type conversions for some functions for Synopsys
Design Compiler. This code gives no trouble for simulation tools or even a
FPGA tool (Altera Quartus).

Here is a relevant snippet:

type row_bound_array is array(natural range <&gt of
std_ulogic_vector(7 downto 0);
subtype num_mem_regions is unsigned(6 downto 0);

-- Find the ratios of the row sizes
procedure find_min_sum(constant drb_array : in row_bound_array;
variable sum : out num_mem_regions;
variable min_size : out num_mem_regions) is
variable temp, temp_min : num_mem_regions;
begin
-- Find smallest row
temp_min := unsigned(drb_array(drb_array'low)(6 downto 0));
for i in drb_array'low + 1 to drb_array'high loop
temp := unsigned(drb_array(i)(6 downto 0)) -
unsigned(drb_array(i-1)(6 downto 0));
if(temp < temp_min) then
temp_min := temp;
end if;
end loop;
min_size := temp_min;

-- Calculate sum of ratios = sum of sizes / minimum row size
sum := (others=>'0');
for i in drb_array'high downto drb_array'low loop
if(unsigned(drb_array(i)(6 downto 0)) > 0) then
sum := unsigned(drb_array(i)(6 downto 0)) / --PROBLEM
temp_min;

The error message I get on the problem line is:

Type mismatch on left and/or right operand of binary operator. (VSS-523)

This occurs for another instance of using the '/' operator and the 'mod'
operator. Is there any way to fix this (does it need fixing or is it a bug in
the tool)? As far as I can tell, this should work because 'num_mem_regions'
is a subtype of unsigned and '/' and 'mod' are defined for unsigned arguments.

 

[Mike Treseler]

gthorpe_at_@ee.ryerson.ca wrote:

I am having trouble with type conversions for some functions for Synopsys
Design Compiler. This code gives no trouble for simulation tools or even a
FPGA tool (Altera Quartus).
Here is a relevant snippet:
procedure find_min_sum(constant drb_array : in row_bound_array;
....
-- Calculate sum of ratios = sum of sizes / minimum row size
sum := (others=>'0');
for i in drb_array'high downto drb_array'low loop
if(unsigned(drb_array(i)(6 downto 0)) > 0) then
sum := unsigned(drb_array(i)(6 downto 0)) / --PROBLEM
temp_min;

I see no syntax or type problem.
If you want synopsis or leo synthesis, you will have
to change the division to a fixed
point multiply. Quartus can sometimes fit
an lpm divide or mod for Altera devices.

The error message I get on the problem line is:
Type mismatch on left and/or right operand of binary operator. (VSS-523)

The problem is not really a type mismatch,
but nevertheless, the functions '/' and "mod"
are not generally synthesizable by multivendor tools.

-- Mike Treseler