type conversation problems

O

Olaf Petzold

Guest
Hi,

I've try to synthesize the following code in a package:

type bitwidth_t is ( -- config fields = 3
BIT_WIDTH_8,
BIT_WIDTH_16,
BIT_WIDTH_24,
BIT_WIDTH_32,
BIT_WIDTH_40,
BIT_WIDTH_48,
BIT_WIDTH_56,
BIT_WIDTH_64
);

type num_sram_t is ( -- config fields = 2
SRAM_N0, -- internal used (FPGA)
SRAM_N1, -- external sram = 1
SRAM_N2, -- external sram = 2
SRAM_N3 -- external sram = 3
);

subtype pcb_ver_t is std_logic_vector(2 downto 0);

type my_info_t is
record
bit_width : bitwidth_t; -- fields=3
num_of_sram : num_sram_t; -- fields=2
pcb_ver : pcb_ver_t; -- fields=3
end record;

constant MY_CONF_FIELD_WIDTH : positive := (bitwidth_t'high +
num_sram_t'high + pcb_ver_t'high); -- Line 51

and got the error:
Line 51. + can not have such operands in this context.

writing:

constant MY_CONF_FIELD_WIDTH : positive
:= unsigned(bitwidth_t'high) + unsigned(num_sram_t'high)
+ unsigned(pcb_ver_t'high);

doesn't solve it:
Line 51. The expression can not be converted to type unsigned.

Similar types (integer etc.) got the same results. How can I add these?

Thanks and Regards,
Olaf
 
the problem goes further:

entity my_config is
port(
hw_conf_field : in std_logic_vector(7 downto 0);
has : out my_config_t;
error : out std_logic
);
end la_config;


architecture behavioral of la_config is

begin

conf_proc: process(hw_conf_field)
begin
has.bit_width <= hw_conf_field(2 downto 0); -- line 47
has.pcb_ver <= hw_conf_field(6 downto 3);
has.num_sram <= hw_conf_field(8 downto 7);
end process;

end behavioral;


I've got errors:

Line 47. Type of . is incompatible with type of hw_conf_field.
Line 48. Size of hw_conf_field is different than size of the target.
Line 49. Type of . is incompatible with type of hw_conf_field.

Thanks
Olaf
 
The types you have defined are in no way similar to type unsigned or
integer. You cannot do a type cast between dissimilar types. I cannot
understand why you would want to use an enumerated type to represent a
number in this case. If you need numeric values for bit_width and
num_of_sram then why not use type positive or subtypes of type
positive? Then you will have no need for conversions.

Charles
 
Hi,

The types you have defined are in no way similar to type unsigned or
integer. You cannot do a type cast between dissimilar types. I cannot
understand why you would want to use an enumerated type to represent a
number in this case. If you need numeric values for bit_width and
num_of_sram then why not use type positive or subtypes of type
positive? Then you will have no need for conversions.
Click to expand...
I guess you mean enums like BIT_WIDTH_8 etc. BW=64 would need 6 macro
cells to represents the 64; using this enums uses (for these 8 values)
3 macro cells. So, this is an optimization for a CPLD. I do have of
similars a lot here.

The idea behind is for principle:


package la_pkg is

subtype pcb_ver_t is std_logic_vector(2 downto 0);

type num_sram_t is ( -- config fields = 2
SRAM_N0, -- internal used (FPGA)
SRAM_N1, -- external sram = 1 -- option #1
SRAM_N2, -- external sram = 2 -- option #2
SRAM_N3 -- external sram = 3
);

type la_config_t is
record
pcb_ver : pcb_ver_t; -- I/O fields=3
num_sram : num_sram_t; -- I/O fields=2
end record;

...

-- won't work
constant LA_CONF_FIELD_WIDTH : positive
:= (num_sram_t'high) + (pcb_ver_t'high);

end la_pkg;



entity la_config is
port(
hw_conf_field : in std_logic_vector(LA_CONF_FIELD_WIDTH-1 downto
0);
has : out la_config_t;
error : out std_logic
);
end la_config;


architecture behavioral of la_config is
begin

conf_proc: process(hw_conf_field)
begin

...
has.pcb_ver <= hw_conf_field(5 downto 3); -- works
has.num_sram <= hw_conf_field(7 downto 6); -- don't

-- check for misc configurations
error <= '0';

end process;

end behavioral;


Thanks and Regards,
Olaf
 
I did wrote the conversation function:

function to_bitwidth(vec : std_logic_vector) return bitwidth_t is
variable bw : bitwidth_t;
begin
case to_integer(vec) is -- LINE 137
when x"0" => bw := BIT_WIDTH_8;
when x"1" => bw := BIT_WIDTH_16;
when x"2" => bw := BIT_WIDTH_24;
when x"3" => bw := BIT_WIDTH_32;
when x"4" => bw := BIT_WIDTH_40;
when x"5" => bw := BIT_WIDTH_48;
when x"6" => bw := BIT_WIDTH_56;
when x"7" => bw := BIT_WIDTH_64;
-- avoid xst error, all bitwidth are handled.
when others => bw := BIT_WIDTH_64;
end case;
return bw;
end;


and got: Line 137. to_integer can not have such operands in this context.

without to_integer() I've got: Line 137. Selector (Constant 'vec' of
type std_logic_vector) is an unconstrained array.

How can I get working this?

Thanks and Regards,
Olaf
 
Hi,

the convert function won't comile:

type bitwidth_t is ( -- config fields = 3
BIT_WIDTH_8,
BIT_WIDTH_16,
BIT_WIDTH_24,
BIT_WIDTH_32,
BIT_WIDTH_40,
BIT_WIDTH_48,
BIT_WIDTH_56,
BIT_WIDTH_64
);

...

function to_bitwidth(vec : std_logic_vector) return bitwidth_t is
variable bw : bitwidth_t;
begin
case (vec) is -- LINE 137
when x"0" => bw := BIT_WIDTH_8;
when x"1" => bw := BIT_WIDTH_16;
when x"2" => bw := BIT_WIDTH_24;
when x"3" => bw := BIT_WIDTH_32;
when x"4" => bw := BIT_WIDTH_40;
when x"5" => bw := BIT_WIDTH_48;
when x"6" => bw := BIT_WIDTH_56;
when x"7" => bw := BIT_WIDTH_64;
-- avoid xst error, all bitwidth are handled.
when others => bw := BIT_WIDTH_64;
end case;
return bw;
end;

Line 137. Selector (Constant 'vec' of type std_logic_vector) is
an unconstrained array.

with to_integer(vec) I've got:
Line 137. to_integer can not have such operands in this context.

How can I solve this?

Thanks
Olaf
 
Olaf Petzold wrote:
the convert function won't comile:
Line 137. Selector (Constant 'vec' of type std_logic_vector) is
an unconstrained array.
Click to expand...
See constrained vec below.

Line 137. to_integer can not have such operands in this context.
to_integer works on unsigned. See below.

-- Mike Treseler
Click to expand...
___________________________________________________________
-- file num_type.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity num_type is
end num_type;

architecture sim of num_type is
begin
what : process is
constant config_fields : natural := 3;
type bitwidth_t is (
BIT_WIDTH_8,
BIT_WIDTH_16,
BIT_WIDTH_24,
BIT_WIDTH_32,
BIT_WIDTH_40,
BIT_WIDTH_48,
BIT_WIDTH_56,
BIT_WIDTH_64
);
function to_bitwidth(vec_arg : std_logic_vector)
return bitwidth_t is
variable bw : bitwidth_t;
subtype case_t is unsigned(config_fields-1 downto 0);
constant vec : case_t := unsigned(vec_arg);
begin
case to_integer(vec) is -- LINE 137
when 0 => bw := BIT_WIDTH_8;
when 1 => bw := BIT_WIDTH_16;
when 2 => bw := BIT_WIDTH_24;
when 3 => bw := BIT_WIDTH_32;
when 4 => bw := BIT_WIDTH_40;
when 5 => bw := BIT_WIDTH_48;
when 6 => bw := BIT_WIDTH_56;
when 7 => bw := BIT_WIDTH_64;
when others => bw := BIT_WIDTH_64;
end case;
return bw;
end;
begin -- process
assert to_bitwidth("110") = BIT_WIDTH_56
report "to_bitwidth: error case 6";
report"test complete. No assertions expected above";
wait;
end process what;
end sim;

-- Sample run:
--# vsim -c num_type
--# Loading /steptoe/usr1/modeltech/linux/../ieee.std_logic_1164(body)
--# Loading /steptoe/usr1/modeltech/linux/../ieee.numeric_std(body)
--# Loading work.num_type(sim)
--VSIM 1> run
--# ** Note: test complete. No assertions expected above
--# Time: 0 ns Iteration: 0 Instance: /num_type
--VSIM 2>
 
Mike Treseler schrieb:
Olaf Petzold wrote:

the convert function won't comile:
Line 137. Selector (Constant 'vec' of type std_logic_vector) is
an unconstrained array.


See constrained vec below.

Line 137. to_integer can not have such operands in this context.

to_integer works on unsigned. See below.


-- Mike Treseler
___________________________________________________________
-- file num_type.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity num_type is
end num_type;

architecture sim of num_type is
begin
what : process is
constant config_fields : natural := 3;
type bitwidth_t is (
BIT_WIDTH_8,
BIT_WIDTH_16,
BIT_WIDTH_24,
BIT_WIDTH_32,
BIT_WIDTH_40,
BIT_WIDTH_48,
BIT_WIDTH_56,
BIT_WIDTH_64
);
function to_bitwidth(vec_arg : std_logic_vector)
return bitwidth_t is
variable bw : bitwidth_t;
subtype case_t is unsigned(config_fields-1 downto 0);
constant vec : case_t := unsigned(vec_arg);
begin
case to_integer(vec) is -- LINE 137
when 0 => bw := BIT_WIDTH_8;
when 1 => bw := BIT_WIDTH_16;
when 2 => bw := BIT_WIDTH_24;
when 3 => bw := BIT_WIDTH_32;
when 4 => bw := BIT_WIDTH_40;
when 5 => bw := BIT_WIDTH_48;
when 6 => bw := BIT_WIDTH_56;
when 7 => bw := BIT_WIDTH_64;
when others => bw := BIT_WIDTH_64;
end case;
return bw;
end;
begin -- process
assert to_bitwidth("110") = BIT_WIDTH_56
report "to_bitwidth: error case 6";
report"test complete. No assertions expected above";
wait;
end process what;
end sim;

-- Sample run:
--# vsim -c num_type
--# Loading /steptoe/usr1/modeltech/linux/../ieee.std_logic_1164(body)
--# Loading /steptoe/usr1/modeltech/linux/../ieee.numeric_std(body)
--# Loading work.num_type(sim)
--VSIM 1> run
--# ** Note: test complete. No assertions expected above
--# Time: 0 ns Iteration: 0 Instance: /num_type
--VSIM 2
Click to expand...
Thanks!

It took my a lot of time to find an incompatibility with
ieee.std_logic_arith.all, which I need for the following:

subtype firmware_t is std_logic_vector(7 downto 0);
constant LA_FIRMWARE_VERSION : firmware_t
:= conv_std_logic_vector(1, firmware_t'length);

Is there a way to combine this, or to replace the firmware stuff with
another implementation/code?

Thanks
Olaf
 
Olaf Petzold wrote:

Thanks!
It took my a lot of time to find an incompatibility with
ieee.std_logic_arith.all, which I need for the following:
Click to expand...
eliminate std_logic_arith
use numeric_std.to_unsigned. See below

-- Mike Treseler

__________________________________________

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity num_type is
end num_type;

architecture sim of num_type is
begin
what : process is
subtype firmware_t is unsigned(7 downto 0);
constant LA_FIRMWARE_VERSION : firmware_t
:= to_unsigned(1, firmware_t'length);
constant config_fields : natural := 3;
type bitwidth_t is (
BIT_WIDTH_8,
BIT_WIDTH_16,
BIT_WIDTH_24,
BIT_WIDTH_32,
BIT_WIDTH_40,
BIT_WIDTH_48,
BIT_WIDTH_56,
BIT_WIDTH_64
);
function to_bitwidth(vec_arg : std_logic_vector)
return bitwidth_t is
variable bw : bitwidth_t;
subtype case_t is unsigned(config_fields-1 downto 0);
constant vec : case_t := unsigned(vec_arg);
begin
case to_integer(vec) is -- LINE 137
when 0 => bw := BIT_WIDTH_8;
when 1 => bw := BIT_WIDTH_16;
when 2 => bw := BIT_WIDTH_24;
when 3 => bw := BIT_WIDTH_32;
when 4 => bw := BIT_WIDTH_40;
when 5 => bw := BIT_WIDTH_48;
when 6 => bw := BIT_WIDTH_56;
when 7 => bw := BIT_WIDTH_64;
when others => bw := BIT_WIDTH_64;
end case;
return bw;
end;
begin -- process
assert to_bitwidth("110") = BIT_WIDTH_56
report "to_bitwidth: error case 6";
assert LA_FIRMWARE_VERSION = "00000001"
report "to_bitwidth: error in version";
report"test complete. No assertions expected above";
wait;
end process what;
end sim;

-- Sample run:
--# vsim -c num_type
--# Loading /steptoe/usr1/modeltech/linux/../ieee.std_logic_1164(body)
--# Loading /steptoe/usr1/modeltech/linux/../ieee.numeric_std(body)
--# Loading work.num_type(sim)
--VSIM 1> run
--# ** Note: test complete. No assertions expected above
--# Time: 0 ns Iteration: 0 Instance: /num_type
--VSIM 2>
 
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