type casting / conversion again

[Shannon]

I struggle with this more than any other subject in VHDL.

Ok... from a post by Jonathan Bromley from some time ago:

acc <= ('0' & acc(7 downto 0)) + amplitude + acc(8);

acc : std_logic_vector(8 downto 0);
amplitude : std_logic_vector(7 downto 0);

it's such a beautiful line of code to accomplish pwm (DeltaSigma
modulator). I would love to keep it as it is without piles of type
conversion and casting and what not but alas I don't think that's
possible. I've tried all kinds of very unclever combinations of
unsigned' this and to_integer that....no glory. Can anyone help?

Shannon (struggling with the same issues over and over again)

 

[Shannon]

On Oct 20, 1:02 pm, Shannon <sgo...@sbcglobal.net> wrote:

I struggle with this more than any other subject in VHDL.

Ok... from a post by Jonathan Bromley from some time ago:

acc <= ('0' & acc(7 downto 0)) + amplitude + acc(8);

acc : std_logic_vector(8 downto 0);
amplitude : std_logic_vector(7 downto 0);

it's such a beautiful line of code to accomplish pwm (DeltaSigma
modulator).  I would love to keep it as it is without piles of type
conversion and casting and what not but alas I don't think that's
possible.  I've tried all kinds of very unclever combinations of
unsigned' this and to_integer that....no glory.  Can anyone help?

Shannon (struggling with the same issues over and over again)

I should mention that I prefer if acc and amplitude were unsigned.
This makes the only problem with that line the "+ acc(8)" part. Is
there a way to convert std_ulogic to unsigned?

Shannon

 

[backhus]

On 20 Okt., 22:53, Shannon <sgo...@sbcglobal.net> wrote:

On Oct 20, 1:02 pm, Shannon <sgo...@sbcglobal.net> wrote:



I struggle with this more than any other subject in VHDL.

Ok... from a post by Jonathan Bromley from some time ago:

acc <= ('0' & acc(7 downto 0)) + amplitude + acc(8);

acc : std_logic_vector(8 downto 0);
amplitude : std_logic_vector(7 downto 0);

it's such a beautiful line of code to accomplish pwm (DeltaSigma
modulator).  I would love to keep it as it is without piles of type
conversion and casting and what not but alas I don't think that's
possible.  I've tried all kinds of very unclever combinations of
unsigned' this and to_integer that....no glory.  Can anyone help?

Shannon (struggling with the same issues over and over again)

I should mention that I prefer if acc and amplitude were unsigned.
This makes the only problem with that line the "+ acc(8)" part.  Is
there a way to convert std_ulogic to unsigned?

Shannon

Hi Shannon,
besides numeric_std there's another library available (since
VHDL-2008):
numeric_std_unsigned

You may try to use this with your tools. In case it won't work, maybe
it's predecessor works for you:
numeric_unsigned

Search the net for the sources and you can work with
std_logic(_vector) just like they were unsigned.
Goody ol' std_logic_unsigned did a similar thing, and because we liked
it so much numeric_std_unsigned is now part of the standard.

Have a nice synthesis
Eilert

 

[Tricky]

On Oct 20, 9:53 pm, Shannon <sgo...@sbcglobal.net> wrote:

On Oct 20, 1:02 pm, Shannon <sgo...@sbcglobal.net> wrote:



I struggle with this more than any other subject in VHDL.

Ok... from a post by Jonathan Bromley from some time ago:

acc <= ('0' & acc(7 downto 0)) + amplitude + acc(8);

acc : std_logic_vector(8 downto 0);
amplitude : std_logic_vector(7 downto 0);

it's such a beautiful line of code to accomplish pwm (DeltaSigma
modulator).  I would love to keep it as it is without piles of type
conversion and casting and what not but alas I don't think that's
possible.  I've tried all kinds of very unclever combinations of
unsigned' this and to_integer that....no glory.  Can anyone help?

Shannon (struggling with the same issues over and over again)

I should mention that I prefer if acc and amplitude were unsigned.
This makes the only problem with that line the "+ acc(8)" part.  Is
there a way to convert std_ulogic to unsigned?

Shannon

you're going to need 1 type conversion, because acc(8) is a not an
array, whereas an unsigned type is.
To make it an array you will need:

unsigned("" & acc(8) ); --this creates a 1 element long array ie.
unsigned(0 downto 0);

you could always put it into a temporary signal to avoid type
conversions on the single line.

 

[Allan Herriman]

On Thu, 21 Oct 2010 00:09:32 -0700, Tricky wrote:

On Oct 20, 9:53 pm, Shannon <sgo...@sbcglobal.net> wrote:
On Oct 20, 1:02 pm, Shannon <sgo...@sbcglobal.net> wrote:



I struggle with this more than any other subject in VHDL.

Ok... from a post by Jonathan Bromley from some time ago:

acc <= ('0' & acc(7 downto 0)) + amplitude + acc(8);

acc : std_logic_vector(8 downto 0);
amplitude : std_logic_vector(7 downto 0);

it's such a beautiful line of code to accomplish pwm (DeltaSigma
modulator).  I would love to keep it as it is without piles of type
conversion and casting and what not but alas I don't think that's
possible.  I've tried all kinds of very unclever combinations of
unsigned' this and to_integer that....no glory.  Can anyone help?

Shannon (struggling with the same issues over and over again)

I should mention that I prefer if acc and amplitude were unsigned. This
makes the only problem with that line the "+ acc(8)" part.  Is there a
way to convert std_ulogic to unsigned?

Shannon

you're going to need 1 type conversion, because acc(8) is a not an
array, whereas an unsigned type is.
To make it an array you will need:

unsigned("" & acc(8) ); --this creates a 1 element long array ie.
unsigned(0 downto 0);

wouldn't acc(8 downto 8) do just as well?

as in:

acc : unsigned(8 downto 0);
amplitude : unsigned(7 downto 0);

acc <= ('0' & acc(7 downto 0)) + amplitude + acc(8 downto 8);

This didn't give any syntax errors under the old version of Modelsim I have on this machine.

Regards,
Allan

 

[Jonathan Bromley]

On Wed, 20 Oct 2010 13:02:41 -0700 (PDT), Shannon wrote:

Ok... from a post by Jonathan Bromley from some time ago:

acc <= ('0' & acc(7 downto 0)) + amplitude + acc(8);

acc : std_logic_vector(8 downto 0);
amplitude : std_logic_vector(7 downto 0);

sheesh, did I really write that? Out of context?
I've been campaigning _against_ the use of
std_logic_unsigned for years, and now it turns out
I've been virally promoting it all that time

it's such a beautiful line of code to accomplish pwm (DeltaSigma
modulator).

The end-around-carry is a very neat trick, yes.
I claim no originality.

As others have said, it will work just fine if
acc and amplitude are both "unsigned", except
that you need to make the carry-in be a 1-bit
vector. acc(8 downto 8) is the easiest, I think.
Other possibilities include

unsigned'(0=>acc(8))
("0" & acc(8))

While we're thinking about alternatives, perhaps
parameterizing the vectors would be good:

[port] amplitude: in unsigned -- unconstrained
...
signal acc: unsigned(amplitude'length downto 0);
...
acc <= ('0' & acc(acc'length-2 downto 0))
+ amplitude + acc(acc'length downto acc'length);
--
Jonathan Bromley

 

[Shannon]

  acc <= ('0' & acc(acc'length-2 downto 0))
       + amplitude + acc(acc'length downto acc'length);
--
Jonathan Bromley

Ahem....and that looks as beautiful as the original to you? (just
teasing). Thank you all for the help. To get through the day I made
a separate signal called 'carry' that handled the conversion to an
array. I'll go back and retry with the acc(8 downto 8) "trick".

I've been campaigning _against_ the use of
std_logic_unsigned for years, and now it turns out
I've been virally promoting it all that time

This is the reason I ask dumb questions... what do you mean by
"std_logic_unsigned"? does this mean I shouldn't be using unsigned?
I use it everywhere!

Shannon

 

[Brian Drummond]

On Thu, 21 Oct 2010 15:07:19 -0700 (PDT), Shannon <sgomes@sbcglobal.net> wrote:

I've been campaigning _against_ the use of
std_logic_unsigned for years, and now it turns out
I've been virally promoting it all that time

This is the reason I ask dumb questions... what do you mean by
"std_logic_unsigned"? does this mean I shouldn't be using unsigned?
I use it everywhere!

No, it means the best way to use "unsigned" is to get it from numeric_std
instead. (Ditto signed)

- Brian

 

[Tricky]

On Oct 21, 11:07 pm, Shannon <sgo...@sbcglobal.net> wrote:

  acc <= ('0' & acc(acc'length-2 downto 0))
       + amplitude + acc(acc'length downto acc'length);
--
Jonathan Bromley

Ahem....and that looks as beautiful as the original to you?   (just
teasing).  Thank you all for the help.  To get through the day I made
a separate signal called 'carry' that handled the conversion to an
array.  I'll go back and retry with the acc(8 downto 8) "trick".

I've been campaigning _against_ the use of
std_logic_unsigned for years, and now it turns out
I've been virally promoting it all that time

This is the reason I ask dumb questions...  what do you mean by
"std_logic_unsigned"?  does this mean I shouldn't be using unsigned?
I use it everywhere!

Shannon

Std_logic_unsigned is a non-IEEE package that lets you treat
std_logic_vectors as unsigned numbers. It was written by Synopsys
about 20 year ago. Unfortunatly, because it was released before the
IEEE standard numeric_std, there are many text books and examples that
use it, and it becomes a vicious circle as new engineers learn from
old text books then recommend the same books to the next generation.
Many many experienced engineers use it too. Its in such a situation
that in the 2008 standard it got rolled into an IEEE standard.

So - dont use it and keep this newsgroup happy

 

[Jonathan Bromley]

On Oct 21, 11:07 pm, Shannon <sgo...@sbcglobal.net> wrote:

  acc <= ('0' & acc(acc'length-2 downto 0))
       + amplitude + acc(acc'length downto acc'length);

Ahem....and that looks as beautiful as the original to you?

Tee hee. No, it's horrid-looking, you're right. But it's
less likely to need life-support in the future.

Aliases might be your friend here...

alias acc_MSB_value: unsigned (0 downto 0)
is acc(acc'left downto acc'left);
alias acc_without_MSB: unsigned(acc'length-2 downto 0)
is acc(acc'length-2 downto 0);
....
acc <= ('0' & acc_without_MSB) + amplitude + acc_MSB_value;

Beauty restored
--
Jonathan Bromley

 

[rickman]

On Oct 22, 4:42 am, Jonathan Bromley <s...@oxfordbromley.plus.com>
wrote:

On Oct 21, 11:07 pm, Shannon <sgo...@sbcglobal.net> wrote:

  acc <= ('0' & acc(acc'length-2 downto 0))
       + amplitude + acc(acc'length downto acc'length);

Ahem....and that looks as beautiful as the original to you?

Tee hee.  No, it's horrid-looking, you're right.  But it's
less likely to need life-support in the future.

Aliases might be your friend here...

  alias acc_MSB_value: unsigned (0 downto 0)
         is acc(acc'left downto acc'left);
  alias acc_without_MSB: unsigned(acc'length-2 downto 0)
         is acc(acc'length-2 downto 0);
...
  acc <= ('0' & acc_without_MSB) + amplitude + acc_MSB_value;

Beauty restored
--
Jonathan Bromley

I believe the original version is not only ugly (the woes of VHDL type
conversions), but it is wrong. Shouldn't part of this be
acc(acc'length-1 downto acc'length-1) ?

I normally use name'high in this context. But considering 'high vs.
'left, I wouldn't know where the trade-offs are. I guess 'high may
not be correct if numbered 0..N which is possible. 'left would not
work if the msb is not left, but that wouldn't be compatible with
unsigned would it?

Rick

 

[Jonathan Bromley]

On Oct 22, 12:33 pm, rickman <gnu...@gmail.com> wrote:

I believe the original version is not only ugly (the woes of VHDL type
conversions), but it is wrong.  Shouldn't part of this be
acc(acc'length-1 downto acc'length-1) ?

Yes - good catch. Sorry.

I normally use name'high in this context.  
But considering 'high vs. 'left, I wouldn't
know where the trade-offs are.  I guess 'high may
not be correct if numbered 0..N which is possible.
 'left would not work if the msb is not left, but
that wouldn't be compatible with unsigned would it?

Yes, the MSB is always 'left and I probably should have
used that. However, there's still another potential
goof because when writing
acc(acc'left downto acc'left)
you need to choose "to" or "downto" based on the original
declaration of acc. However, if you get that wrong the compiler
will pick it up.

I wish it were possible to declare unconstrained arrays
in VHDL with the to/downto direction constrained:

type jonathans_unsigned is array(natural range &gt of ...

(where "range <>" allows both to/downto, "range >" allows
only downto, "range <" allows only to) so that it would
then be illegal to declare any jonathans_unsigned with
a "to" direction. But it is not so :-(

The standard defence against being given an array that
might have inappropriate direction is to copy or alias
it onto an array whose subscript range you've normalized.
I'm pretty paranoid about always doing that in real code,
but I got sloppy in this morning's post.

Thanks

Jonathan