Tying two wires together

Guest
I have a setup where there are two wires one for input to a module and
the other for output from this module. The two wires are tied together
outside of the module to form a single serial line, and then fed to a
bi-directional buffer with a direction control input. How can I model
this setup? Normally when the buffer is in the input mode the input
pin will receive what is on the other side of the buffer but if the
output is not high impedance at the same time this is happening, a
contention will happen. I would like to detect that contention. Right
now I'm using the following process to model this behavior but I
wonder if there's a better way to do it that represents the physical
connection and that does not require me to explicitly assign 'X' to
the line.

PROCESS (data_en, target, sdi, sdo)
BEGIN
IF (data_en = '1') THEN
target <= sdo;
sdi <= sdo;
ELSE
IF (sdo = 'Z') THEN
sdi <= target;
ELSE
sdi <= 'X';
END IF;
END IF;
END PROCESS;

The bidirectional buffer here is not physically represented but
implied from the process.

any help is appreciated

Thank you!
 
It depends on your simulation tools. ModelSim will detect contention
of a signal having 2 drivers in VHDL and will assign it a U
(undefined).
 
"D Stanford" <David.Stanford@gmail.com> writes:

It depends on your simulation tools. ModelSim will detect contention
of a signal having 2 drivers in VHDL and will assign it a U
(undefined).
Click to expand...
This is tool independent. If you have two (or more) drivers on a
signal, they will resolve to values depending on the type of the
signal.

For std_logic, you'll get an 'X' if you drive a '0' from one and a '1'
from another. 'U' is reserved for "uninitialised".

Cheers,
Martin


--
martin.j.thompson@trw.com
TRW Conekt - Consultancy in Engineering, Knowledge and Technology
http://www.conekt.net/electronics.html
 
mhs000@gmail.com writes:

I have a setup where there are two wires one for input to a module and
the other for output from this module. The two wires are tied together
outside of the module to form a single serial line, and then fed to a
bi-directional buffer with a direction control input. How can I model
this setup? Normally when the buffer is in the input mode the input
pin will receive what is on the other side of the buffer but if the
output is not high impedance at the same time this is happening, a
contention will happen. I would like to detect that contention. Right
now I'm using the following process to model this behavior but I
wonder if there's a better way to do it that represents the physical
connection and that does not require me to explicitly assign 'X' to
the line.
Click to expand...
I don't think you need to be that complex - just tie the signals
together and the simulator will resolve them for you. If you drive Z
and a 1 or 0, the 1 or 0 will dominate, otherwise you'll get X:

Assuming your target drives on the one wire, a model of your
tristatable buffer would be:
target <= sdo when enable = '1' else 'Z';
sdi <= target;

This ought to work if I understand your setup correctly...

Cheers,
Martin

--
martin.j.thompson@trw.com
TRW Conekt - Consultancy in Engineering, Knowledge and Technology
http://www.conekt.net/electronics.html
 
Thanks for the responses. To model the bidirectional buffer, I did:

target <= sdisdo WHEN data_en = '1' ELSE 'Z';
sdisdo <= target WHEN data_en = '0' ELSE 'Z';

And to model the two wires tied together, I did :

sdisdo <= sdo;
sdi <= sdisdo;

Where sdisdo is a signal i declared to represent the junction, and sdi
and sdo are the input and output ports. This seems to work.
 
On 26 mar, 14:16, mhs...@gmail.com wrote:
Thanks for the responses. To model the bidirectional buffer, I did:

target <= sdisdo WHEN data_en = '1' ELSE 'Z';
sdisdo <= target WHEN data_en = '0' ELSE 'Z';

And to model the two wires tied together, I did :

sdisdo <= sdo;
sdi <= sdisdo;

Where sdisdo is a signal i declared to represent the junction, and sdi
and sdo are the input and output ports. This seems to work.
Click to expand...
I think there is something wrong here... aren't you trying to do this?

+-------+
| |
+--->| module|---+
| | | |
| +-------+ | +----+
| +--->|mux |
---+-------------------->| |------> output
input +----+
^
|
|
|ctrl

Cheers,
weber
 
Here is what I'm trying to do:
enable
|
sdo >---------- ------->-------
| | |
+-----------+ +----------- target
| | |
sdi <---------- -------<-------
|
/enable


On Mar 27, 9:16 am, "weber" <hug...@gmail.com> wrote:
On 26 mar, 14:16, mhs...@gmail.com wrote:

Thanks for the responses. To model the bidirectional buffer, I did:

target <= sdisdo WHEN data_en = '1' ELSE 'Z';
sdisdo <= target WHEN data_en = '0' ELSE 'Z';

And to model the two wires tied together, I did :

sdisdo <= sdo;
sdi <= sdisdo;

Where sdisdo is a signal i declared to represent the junction, and sdi
and sdo are the input and output ports. This seems to work.

I think there is something wrong here... aren't you trying to do this?

+-------+
| |
+--->| module|---+
| | | |
| +-------+ | +----+
| +--->|mux |
---+-------------------->| |------> output
input +----+
^
|
|
|ctrl

Cheers,
weber
Click to expand...
 
mhs000@gmail.com schrieb:
Here is what I'm trying to do:
enable
|
sdo >---------- ------->-------
| | |
+-----------+ +----------- target
| | |
sdi <---------- -------<-------
|
/enable
Click to expand...

Why do you need a transfer gate? You need a tri state output driver:

target<=sdo when (enable='1') else 'Z';

Additionally you have to read the value of the target as input:

sdi<=target;

Nothing more - if I did not miss a point.


Ralf
 
Why do you need a transfer gate? You need a tri state output driver:

target<=sdo when (enable='1') else 'Z';

Additionally you have to read the value of the target as input:

sdi<=target;
Click to expand...
The only problem i see with your approach is that it represent only
one junction at the target:

enable
|
sdo >------------------------------>-------
|
+----------- target
|
sdi <------------------------------<-------
|
/enable

If enable = 1 then the effect is the same, but when enable is 0, i
believe the first approach will detect a contention if both sdo and
target trying to drive the sdi line together, while the second
approach has sdo isolated from sdi and target and will not be able to
detect that situation. This is important for me since the enable bit
is different from the bit that sets sdo to 'Z' or not.
 
mhs000@gmail.com schrieb:

target<=sdo when (enable='1') else 'Z';
sdi<=target;
Click to expand...

The only problem i see with your approach is that it represent only
one junction at the target:

enable
|
sdo >------------------------------>-------
|
+----------- target
|
sdi <------------------------------<-------
|
/enable

If enable = 1 then the effect is the same, but when enable is 0, i
believe the first approach will detect a contention if both sdo and
target trying to drive the sdi line together
Click to expand...
If enable='0' then sdo cannot drive target or sdi.


, while the second
approach has sdo isolated from sdi and target and will not be able to
detect that situation. This is important for me since the enable bit
is different from the bit that sets sdo to 'Z' or not.
Click to expand...
Why do you need /two/ tri-state drivers in a chain?

sdo <= sdo_i when (enable_i='1') else 'z';
target <= sdo when (enable ='1') else 'z';

Do I miss something or is this just a waste of ressources?


Ralf
 
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