twos complement data

[redstripe]

I am working on a GRAPHICAL design in QuartusII where I have data
represented with the twos complement number system. This is not a
problem as most of the time the data is the same bit width (usually 12)
and I preserve the sign and magnitude.

The problem I am having is in a "simple" VHDL section I am trying to
write. There are times when I want to take the 12 bit twos complement
data and limit it to some smaller value (lets say 6bits). So the input
would be 12 bits and the output would be 6 bits. If the 12 bit number
is within the 6 bits it passes through, otherwise it is limited. I am
very new to VHDL and I assumed this task would be simple.

First, is there any easy way to set a 6bit output equal to a 12bit
input? assuming the 12bit data is within the 6 bits? Every time I try
I run into some sort of error.

The next part would be just checking if the 12bit input is out of the 6
bit range and if it is setting the output to the max/min value.

Any help would be greatly appreciated.

 

[Dave Pollum]

redstripe wrote:

I am working on a GRAPHICAL design in QuartusII where I have data
represented with the twos complement number system. This is not a
problem as most of the time the data is the same bit width (usually 12)
and I preserve the sign and magnitude.

The problem I am having is in a "simple" VHDL section I am trying to
write. There are times when I want to take the 12 bit twos complement
data and limit it to some smaller value (lets say 6bits). So the input
would be 12 bits and the output would be 6 bits. If the 12 bit number
is within the 6 bits it passes through, otherwise it is limited. I am
very new to VHDL and I assumed this task would be simple.

First, is there any easy way to set a 6bit output equal to a 12bit
input? assuming the 12bit data is within the 6 bits? Every time I try
I run into some sort of error.

The next part would be just checking if the 12bit input is out of the 6
bit range and if it is setting the output to the max/min value.

Any help would be greatly appreciated.

assuming that "input" and "output" are std_logic_vectors:
input std_logic_vector(11 downto 0)
output std_logic_vector(5 downto 0);
then:
output <= input(5 downto 0); -- should work.

HTH
-Dave Pollum

 

[Ralf Hildebrandt]

Dave Pollum wrote:

output <= input(5 downto 0); -- should work.

And if you need to take care about overflow, you have to monitor the
discarded bits and the sign bit of the result.

overflow<='0' when (input(11 downto 5)="0000000" OR
input(11 downto 5)="1111111") else '1';

Ralf

 

[Andy]

Or, for a little more flexible code, assuming output is smaller than
input and both have descending ranges ending at the same bit (not
necessarily 0):

output <= input(output'range);

This way, as long as the above assumptions are true, you can change the
sizes of input and output, and it still works.

Or do like I do, and use integers; they are much quicker to simulate
too.

Andy