two .vhd sources in a project... ISE 9.1 ?

[jesse lackey]

Sorry for the total newbie dumb questions. It is rather frustrating
that I can't figure it out and am not finding help / docs on this.

I have a project with a single .vhd file. Fine.
I have another module developed and tested in another project, called
"multiplexed_output".
All I want to do is have that module be part of my main project, so I
can start using it.
If I do "add source", it becomes part of the project, and I can do a
"check syntax" on it just fine. However it is not seen by the main
module, so trying to instantiate "multiplexed_output" fails. Undefined
symbol.

I was able to have two files in the project I used to create
"multiplexed_output", the main vhdl code and a testbench in vhdl.
However this was created for me by a wizard in ISE, and now that I have
to do it myself, I'm stuck.

It is probably like 4 mouseclicks, but I could be here all evening. I'd
rather not copy the vhdl code into the one vhdl file I have in the main
project. Modularity and all.

as an aside, I'm really thinking of switching to Altera for the next
design, primarily due to user-unfriendlyness of xilinx tools. Bugs and
crashes and meaningless error messages. Does anyone who has used recent
versions of both have an opinion on this?

Thanks in advance
J

 

[Colin Paul Gloster]

Jesse Lackey posted:
"Sorry for the total newbie dumb questions. It is rather frustrating
that I can't figure it out and am not finding help / docs on this.

I have a project with a single .vhd file. Fine.
I have another module developed and tested in another project, called
"multiplexed_output".
All I want to do is have that module be part of my main project, so I
can start using it.
If I do "add source", it becomes part of the project, and I can do a
"check syntax" on it just fine. However it is not seen by the main
module, so trying to instantiate "multiplexed_output" fails. Undefined
symbol.

I was able to have two files in the project I used to create
"multiplexed_output", the main vhdl code and a testbench in vhdl.
However this was created for me by a wizard in ISE, and now that I have
to do it myself, I'm stuck.

[..]"

Hello,

I can think of two possibilities. Perhaps you did not have ISE analyze
"Multiplexed_output" before you had ISE analyze the main file. I
suspect this is not your problem, but it probably will be if my other
idea is right and you fix that problem...

....I suggest that you check in your main file whether you are missing
a LIBRARY or USE keyword which you would need in order to import the
other file's "Multiplexed_output". Check how this is done in the
original project created by the wizard.

"[..]
crashes and meaningless error messages. [..]"

Everyone will find many error messages from all tools unsuitable. This
is not the fault of the tools. Some people try a lot to provide very
helpful error messages which will be very helpful when the advice is
appropiate, but not when it is not and it will not be right in general
even if it is usually right so I completely respect people who do not
bother.

An example...

entity confusing is
Port ( C_programmers_are_stupid : out integer;
different_people_interpret_things_differently_so_need_different_advice : in integer
);
end confusing;

architecture Behavioral of confusing is

begin
C_programmers_are_stupid
/= --"ERROR:HDLParsers:164 - //lothlorien/dati/error_messages/confusing.vhd Line 11. parse error, unexpected NOTEQ, expecting OPENPAR or TICK or LSQBRACK".
different_people_interpret_things_differently_so_need_different_advice;
end Behavioral;

The programmers of ISE can not know that someone is trying to use the
/= operator of C which is in no way similar to the /= operator of
VHDL. ISE does however point out that a problem may exist with the
attempt to use /=.

Regards,
Colin Paul Gloster

 

[Newman]

On May 30, 8:33 pm, jesse lackey <j...@celestialaudio.com> wrote:

Sorry for the total newbie dumb questions. It is rather frustrating
that I can't figure it out and am not finding help / docs on this.

I have a project with a single .vhd file. Fine.
I have another module developed and tested in another project, called
"multiplexed_output".
All I want to do is have that module be part of my main project, so I
can start using it.
If I do "add source", it becomes part of the project, and I can do a
"check syntax" on it just fine. However it is not seen by the main
module, so trying to instantiate "multiplexed_output" fails. Undefined
symbol.

I was able to have two files in the project I used to create
"multiplexed_output", the main vhdl code and a testbench in vhdl.
However this was created for me by a wizard in ISE, and now that I have
to do it myself, I'm stuck.

It is probably like 4 mouseclicks, but I could be here all evening. I'd
rather not copy the vhdl code into the one vhdl file I have in the main
project. Modularity and all.

as an aside, I'm really thinking of switching to Altera for the next
design, primarily due to user-unfriendlyness of xilinx tools. Bugs and
crashes and meaningless error messages. Does anyone who has used recent
versions of both have an opinion on this?

Thanks in advance
J

Is the multiplex_output module below the main vhdl file in the ISE
source window. If it isn't, ISE thinks they are not connected. I
would carefully check the component and instance declaration in the
main file to see if they match the entity description of the
multiplex_output module.

You might go to the library tab and under work, delete the
multiplex_output entry and re-add it again.

You might open Modelsim, compile the two modules and open a simulation
on the top module. If that doesn't open without error, then the fault
points to something in your code.

Hope this helps,

Newman

 

On May 30, 5:33 pm, jesse lackey <j...@celestialaudio.com> wrote:

Sorry for the total newbie dumb questions. It is rather frustrating
that I can't figure it out and am not finding help / docs on this.

I have a project with a single .vhd file. Fine.
I have another module developed and tested in another project, called
"multiplexed_output".
All I want to do is have that module be part of my main project, so I
can start using it.
If I do "add source", it becomes part of the project, and I can do a
"check syntax" on it just fine. However it is not seen by the main
module, so trying to instantiate "multiplexed_output" fails. Undefined
symbol.

I was able to have two files in the project I used to create
"multiplexed_output", the main vhdl code and a testbench in vhdl.
However this was created for me by a wizard in ISE, and now that I have
to do it myself, I'm stuck.

It is probably like 4 mouseclicks, but I could be here all evening. I'd
rather not copy the vhdl code into the one vhdl file I have in the main
project. Modularity and all.

as an aside, I'm really thinking of switching to Altera for the next
design, primarily due to user-unfriendlyness of xilinx tools. Bugs and
crashes and meaningless error messages. Does anyone who has used recent
versions of both have an opinion on this?

Thanks in advance
J

You need to create a "master file" that "uses" the two files you
mention.

"master file" = top level file
"uses" = instantiates

In other words, create a top level file that instantiates the two
files as components.

G.