two process writing on one signal!

[hakim]

....sorry if this has already been discussed before but i didnt get
nething addressing my exact concern on searching the archives! ...or
was i just too lazy!!
so here goes! I have multiple processes within an architecture of a
VHDl entity that writes to common signals. I understand that this is a
case of multiple drivers and that it is incorrect to have two
processes drive diff values on the signals simultaneously.
but i precisely know how my process executions overlap and am sure
that no two process will drive values at the same time. As in, if one
drives either 0 or 1 on the signal, all others are definitely driving
a 'Z' (or basically tristated).
....and yes it is important for me to keep them as separate processes
and not combine them into a single big process.

How do i pass on this information to the synthesizer to allow it to
complete sythesis process without errors? I am using Xilinx 6.3i for
FPGA syntheis.

Lemme know if u would like to see the code or need more details.

Thanks
Hakim

 

[Rich Webb]

On 9 Oct 2004 21:50:47 -0700, hakimraja@hotmail.com (hakim) wrote:

...sorry if this has already been discussed before but i didnt get
nething addressing my exact concern on searching the archives! ...or
was i just too lazy!!
so here goes! I have multiple processes within an architecture of a
VHDl entity that writes to common signals. I understand that this is a
case of multiple drivers and that it is incorrect to have two
processes drive diff values on the signals simultaneously.
but i precisely know how my process executions overlap and am sure
that no two process will drive values at the same time. As in, if one
drives either 0 or 1 on the signal, all others are definitely driving
a 'Z' (or basically tristated).
...and yes it is important for me to keep them as separate processes
and not combine them into a single big process.

How do i pass on this information to the synthesizer to allow it to
complete sythesis process without errors? I am using Xilinx 6.3i for
FPGA syntheis.

#disclaimer: still learning but having fun

AFAIK, the only way to do this is to have the "single big process" that
you say you don't want. Not sure otherwise how to explicitly control
which gets to change what, when.

...
big_signal : std_logic;
...
big_signal <= this_event or that_event or other_event or ... ;
...
process (reset, big_signal)
...
if reset = '0'
...
elsif big_signal'event and big_signal = '1'
if this_event = '1'
...

and so on.

--
Rich Webb Norfolk, VA