two modules sharing same clock -need help!

[thomasc]

Suppose that we have two modules, "a.v" and "b.v", and that they share a
same clock signal. I thought of two possibilities in such a case.

1) inputting clock signal to "b.v" when instantiating it from "a.v"
2) having a 'ClkGenerator.v' and giving clock directly to both of them
from it

My question is if there is a better method between the above two and if
there is another way that I can implement it in a better way. Please reply
and let me know.

Thank you very much!

thomasc

 

[Neo]

There is nothing to be surprised all modules usually share the same
clock signal. Just port map the clock to each module or assign it to a
signal and use that for a module.

 

[MysticSage]

Hmmm... solution 2 is better.

In real life, ClkGenerator.v will be replaced by PLL.