Two hierarchy designs

V

Verictor

Guest
Hi,

I compare these two hierarchical designs. They are equal in terms of
functionality. However, synthesis results are quite different. The
first one is error and warning clean while the other one has "assign"
warning for "reset" signal. But it never generates warning on "clock"
even though the "clock" signal has been used in the same as the
"reset" signal. I wonder if the "assign" warning is serious and what
other designers handle this.

Of course, the #1 approach is the best but it needs to change
submodule input/output when designing top module. Is Design #2 still a
valid design? Or, is it possible to get rid of the warning, maybe
using synthesis script?

The two design examples are as following:

Design #1: this is synthesis clean. It has 3 separated files: top1.v
top.v and dff.v
// File top1.v
module top1(clock, reset, read, busy);
input clock, reset;
output read, busy;
wire nc;

top
top_inst(.clock(clock), .Reset(reset), .read(read), .busy(busy));
dff dff_inst(.d(1'b0), .clk(clock), .reset(Reset), .q(nc));
endmodule

// File top.v
module top(clock, Reset,read, busy);
input clock, Reset;
output read, busy;

reg read, next_read;
reg busy, next_busy;

reg state, next_state;

always @(posedge clock or negedge reset) begin
if (!reset) begin
state <= 1'b0;
end else begin
state <= next_state;
read <= next_read;
busy <= next_busy;
end
end

endmodule

// File 3: dff.v
module dff(d, reset, clk, q);
input d, reset, clk;
output q;
reg q;

always @(posedge clk or negedge reset) begin
if (!reset)
q <= 1'b0;
else
q <= d;
end

endmodule


Design #2: It has "reset" assignment warning after synthesis. But no
warnings for "clock"!!!

module top(clock, Reset,read, busy);
input clock, Reset;
output read, busy;

reg read, next_read;
reg busy, next_busy;

reg state, next_state;

wire nc;
dff
dff_inst(.d(1'b0), .clock(clock), .reset(reset), .q(nc));

always @(posedge clock or negedge reset) begin
if (!reset) begin
state <= 1'b0;
end else begin
state <= next_state;
read <= next_read;
busy <= next_busy;
end
end

endmodule

module dff(d, clock, reset, q);
input d, clock, reset;
output q;

always @(posedge clock or negedge clk) begin
if (!reset) begin
q <= 1'b0;
end else begin
q <= d;
end
end

endmodule
 
Hi,

The dff module in the second implementation is wrong (reset is missing
from the port map).

Jerome.

Verictor a écrit :
Hi,

I compare these two hierarchical designs. They are equal in terms of
functionality. However, synthesis results are quite different. The
first one is error and warning clean while the other one has "assign"
warning for "reset" signal. But it never generates warning on "clock"
even though the "clock" signal has been used in the same as the
"reset" signal. I wonder if the "assign" warning is serious and what
other designers handle this.

Of course, the #1 approach is the best but it needs to change
submodule input/output when designing top module. Is Design #2 still a
valid design? Or, is it possible to get rid of the warning, maybe
using synthesis script?

The two design examples are as following:

Design #1: this is synthesis clean. It has 3 separated files: top1.v
top.v and dff.v
// File top1.v
module top1(clock, reset, read, busy);
input clock, reset;
output read, busy;
wire nc;

top
top_inst(.clock(clock), .Reset(reset), .read(read), .busy(busy));
dff dff_inst(.d(1'b0), .clk(clock), .reset(Reset), .q(nc));
endmodule

// File top.v
module top(clock, Reset,read, busy);
input clock, Reset;
output read, busy;

reg read, next_read;
reg busy, next_busy;

reg state, next_state;

always @(posedge clock or negedge reset) begin
if (!reset) begin
state <= 1'b0;
end else begin
state <= next_state;
read <= next_read;
busy <= next_busy;
end
end

endmodule

// File 3: dff.v
module dff(d, reset, clk, q);
input d, reset, clk;
output q;
reg q;

always @(posedge clk or negedge reset) begin
if (!reset)
q <= 1'b0;
else
q <= d;
end

endmodule


Design #2: It has "reset" assignment warning after synthesis. But no
warnings for "clock"!!!

module top(clock, Reset,read, busy);
input clock, Reset;
output read, busy;

reg read, next_read;
reg busy, next_busy;

reg state, next_state;

wire nc;
dff
dff_inst(.d(1'b0), .clock(clock), .reset(reset), .q(nc));

always @(posedge clock or negedge reset) begin
if (!reset) begin
state <= 1'b0;
end else begin
state <= next_state;
read <= next_read;
busy <= next_busy;
end
end

endmodule

module dff(d, clock, reset, q);
input d, clock, reset;
output q;

always @(posedge clock or negedge clk) begin
if (!reset) begin
q <= 1'b0;
end else begin
q <= d;
end
end

endmodule
Click to expand...
 
On Mar 8, 3:32 am, Jerome <jeje@.com> wrote:
Hi,

The dff module in the second implementation is wrong (reset is missing
from the port map).

Jerome.

Verictor a écrit :



Hi,

I compare these two hierarchical designs. They are equal in terms of
functionality. However, synthesis results are quite different. The
first one is error and warning clean while the other one has "assign"
warning for "reset" signal. But it never generates warning on "clock"
even though the "clock" signal has been used in the same as the
"reset" signal. I wonder if the "assign" warning is serious and what
other designers handle this.

Of course, the #1 approach is the best but it needs to change
submodule input/output when designing top module. Is Design #2 still a
valid design? Or, is it possible to get rid of the warning, maybe
using synthesis script?

The two design examples are as following:

Design #1: this is synthesis clean. It has 3 separated files: top1.v
top.v and dff.v
// File top1.v
module top1(clock, reset, read, busy);
input clock, reset;
output read, busy;
wire nc;

top
top_inst(.clock(clock), .Reset(reset), .read(read), .busy(busy));
dff dff_inst(.d(1'b0), .clk(clock), .reset(Reset), .q(nc));
endmodule

// File top.v
module top(clock, Reset,read, busy);
input clock, Reset;
output read, busy;

reg read, next_read;
reg busy, next_busy;

reg state, next_state;

always @(posedge clock or negedge reset) begin
if (!reset) begin
state <= 1'b0;
end else begin
state <= next_state;
read <= next_read;
busy <= next_busy;
end
end

endmodule

// File 3: dff.v
module dff(d, reset, clk, q);
input d, reset, clk;
output q;
reg q;

always @(posedge clk or negedge reset) begin
if (!reset)
q <= 1'b0;
else
q <= d;
end

endmodule

Design #2: It has "reset" assignment warning after synthesis. But no
warnings for "clock"!!!

module top(clock, Reset,read, busy);
input clock, Reset;
output read, busy;

reg read, next_read;
reg busy, next_busy;

reg state, next_state;

wire nc;
dff
dff_inst(.d(1'b0), .clock(clock), .reset(reset), .q(nc));

always @(posedge clock or negedge reset) begin
if (!reset) begin
state <= 1'b0;
end else begin
state <= next_state;
read <= next_read;
busy <= next_busy;
end
end

endmodule

module dff(d, clock, reset, q);
input d, clock, reset;
output q;

always @(posedge clock or negedge clk) begin
if (!reset) begin
q <= 1'b0;
end else begin
q <= d;
end
end

endmodule- Hide quoted text -

- Show quoted text -
Click to expand...
Oh, I had a typo. If you could make a simple change, you will see what
I mean, which is more important than that typo.
 
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