two-dimensional arrays cannot be simulated

Guest
Hello all,

I am trying to use a two-dimensional array (inhibitory_weights_array)
in the port of a vhdl program as follows:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

library UNISIM;
use UNISIM.VComponents.all;

library work;
use work.type_definitions.all;

entity tree_adder is
port (
A : in inhibitory_weights_array;
S : out std_logic_vector(15 downto 0)
);
end tree_adder;

architecture Behavioral of tree_adder is

component add_sub
port (
A : IN std_logic_VECTOR(15 downto 0);
B : IN std_logic_VECTOR(15 downto 0);
C_IN : IN std_logic;
C_OUT: OUT std_logic;
ADD : IN std_logic;
S : OUT std_logic_VECTOR(15 downto 0)
);
end component;

signal Partial_sum: inhibitory_weights_array;

constant Logic_0 : std_logic := '0';
constant Logic_1 : std_logic := '1';

begin

adding_weights_input : for i in 0 to 11 generate
first_level : add_sub
port map (
A => A(2*i),
B => A(2*i+1),
C_IN => Logic_0,
C_OUT => OPEN,
ADD => Logic_1,
S => Partial_sum(i)
);
end generate adding_weights_input;

adding_partial_sums : for i in 0 to 5 generate
second_level : add_sub
port map (
A => Partial_sum(2*i),
B => Partial_sum(2*i+1),
C_IN => Logic_0,
C_OUT => OPEN,
ADD => Logic_1,
S => Partial_sum(i+12)
);
end generate adding_partial_sums;

adding_partial2_sums : for i in 0 to 2 generate
third_level : add_sub
port map (
A => Partial_sum(2*i+12),
B => Partial_sum((2*i+12)+1),
C_IN => Logic_0,
C_OUT => OPEN,
ADD => Logic_1,
S => Partial_sum(i+18)
);
end generate adding_partial2_sums;

Fourth_level : add_sub
port map(
A => Partial_sum(18),
B => Partial_sum(19),
C_IN => Logic_0,
C_OUT => OPEN,
ADD => Logic_1,
S => Partial_sum(21)
);

Fourth_level_zeros : add_sub
port map(
A => Partial_sum(20),
B => (others => '0'),
C_IN => Logic_0,
C_OUT => OPEN,
ADD => Logic_1,
S => Partial_sum(22)
);

Last_level : add_sub
port map(
A => Partial_sum(21),
B => Partial_sum(22),
C_IN => Logic_0,
C_OUT => OPEN,
ADD => Logic_1,
S => Partial_sum(23)
);

S <= Partial_sum(23);

end Behavioral;

where inhibitory_weights_array is defined in the package
type_definitions as:

TYPE inhibitory_weights_array IS array(0 to 23) of std_logic_vector(15
downto 0);

the component add_sub was generated by coregen and is in fact an
add/sub 16 bits with carry in, carry out.

Synthesis do not show any error, so I assume the VHDL is correct, but
when I try to check his behavioral simulation, the testbench tool fails
to create the right waveform, making port A as
an array of 24 elements of bit (equivalent to std_logic_vector(23
downto 0)) this can be seen below in the testbench text where A is
defined as:

A : In inhibitory_weights_arrayBase (0 To 23);

The full testbench file is the following:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library UNISIM;
use UNISIM.VComponents.all;
library work;
use work.type_definitions.all;
USE IEEE.STD_LOGIC_TEXTIO.ALL;
USE STD.TEXTIO.ALL;

ENTITY test_weight_Adder IS
END test_weight_Adder;

ARCHITECTURE testbench_arch OF test_weight_Adder IS
FILE RESULTS: TEXT OPEN WRITE_MODE IS "results.txt";

COMPONENT tree_adder
PORT (
A : In inhibitory_weights_arrayBase (0 To 23);
S : Out std_logic_vector (15 DownTo 0)
);
END COMPONENT;

SIGNAL A : inhibitory_weights_arrayBase (0 To 23) :=
"000000000000000000000000";
SIGNAL S : std_logic_vector (15 DownTo 0) := "0000000000000000";

SHARED VARIABLE TX_ERROR : INTEGER := 0;
SHARED VARIABLE TX_OUT : LINE;

BEGIN
UUT : tree_adder
PORT MAP (
A => A,
S => S
);

PROCESS
PROCEDURE CHECK_S(
next_S : std_logic_vector (15 DownTo 0);
TX_TIME : INTEGER
) IS
VARIABLE TX_STR : String(1 to 4096);
VARIABLE TX_LOC : LINE;
BEGIN
IF (S /= next_S) THEN
STD.TEXTIO.write(TX_LOC, string'("Error at
time="));
STD.TEXTIO.write(TX_LOC, TX_TIME);
STD.TEXTIO.write(TX_LOC, string'("ns S="));
IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, S);
STD.TEXTIO.write(TX_LOC, string'(", Expected = "));
IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_S);
STD.TEXTIO.write(TX_LOC, string'(" "));
TX_STR(TX_LOC.all'range) := TX_LOC.all;
STD.TEXTIO.writeline(RESULTS, TX_LOC);
STD.TEXTIO.Deallocate(TX_LOC);
ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
TX_ERROR := TX_ERROR + 1;
END IF;
END;
BEGIN
-- ------------- Current Time: 1000ns
WAIT FOR 1000 ns;
A <= "000000000000000000000000";

IF (TX_ERROR = 0) THEN
STD.TEXTIO.write(TX_OUT, string'("No errors or
warnings"));
STD.TEXTIO.writeline(RESULTS, TX_OUT);
ASSERT (FALSE) REPORT
"Simulation successful (not a failure). No
problems detected."
SEVERITY FAILURE;
ELSE
STD.TEXTIO.write(TX_OUT, TX_ERROR);
STD.TEXTIO.write(TX_OUT,
string'(" errors found in simulation"));
STD.TEXTIO.writeline(RESULTS, TX_OUT);
ASSERT (FALSE) REPORT "Errors found during
simulation"
SEVERITY FAILURE;
END IF;
END PROCESS;

END testbench_arch;


I have tried several options, for example I changed the entity to:

entity tree_adder is
port (
B0 : in std_logic_vector(15 downto 0);
B1 : in std_logic_vector(15 downto 0);
. . .
.
. . .
.
. . .
.
B23 : in std_logic_vector(15 downto 0);
S : out std_logic_vector(15 downto 0)
);
end tree_adder;

and then defining a signal (after architecture)

signal A : inhibitory_weights_array;

begin
A(0) <= B0;

and so on.

And it didn't work either, it seems ISE has problems dealing with
multidimensional arrays. So ISE is unable to create he right testbench
file to my entity, as a consequence, it is impossible to run a
simulation or even find a bug in the program.

Another problem came when I tried to create the RTL schematic, for the
entity, well I was able to get the right schematic, I mean a box with
24 inputs, all of them std_logic_vector(15 downto 0), which is correct,
but when I double-click on the RTL to see its internal structure a
pop-up window shows up saying "Xilinx - ISE has encountered a problem
and needs to close. We are sorry for the inconvenience." , just after
clicking the <CLOSE> button, it closes ISE and the project, not just
the pop-up window, so I have to restart ISE. So not even is possible to
check the internal structure of the entity to check if internal
connections are ok, which would give an idea of the correctness of the
program.

I am using ISE 8.1 and both ISE Simulator and Modelsim SE 5.8.

Any help will be greatly appreciated.
Regards,

Ruben
 
Keep in mind you are porting an algorithm that was original writen in a
programming language to a hardware description language, instead of
thinking of 'passing' you should be thinking of 'connecting' or
'sharing'. Instead of doing what you are trying to do why not store the
values in a chunk of memory and connect the address and data bus to
your component.

ruben.gue@gmail.com wrote:
Hello all,

I am trying to use a two-dimensional array (inhibitory_weights_array)
in the port of a vhdl program as follows:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

library UNISIM;
use UNISIM.VComponents.all;

library work;
use work.type_definitions.all;

entity tree_adder is
port (
A : in inhibitory_weights_array;
S : out std_logic_vector(15 downto 0)
);
end tree_adder;

architecture Behavioral of tree_adder is

component add_sub
port (
A : IN std_logic_VECTOR(15 downto 0);
B : IN std_logic_VECTOR(15 downto 0);
C_IN : IN std_logic;
C_OUT: OUT std_logic;
ADD : IN std_logic;
S : OUT std_logic_VECTOR(15 downto 0)
);
end component;

signal Partial_sum: inhibitory_weights_array;

constant Logic_0 : std_logic := '0';
constant Logic_1 : std_logic := '1';

begin

adding_weights_input : for i in 0 to 11 generate
first_level : add_sub
port map (
A => A(2*i),
B => A(2*i+1),
C_IN => Logic_0,
C_OUT => OPEN,
ADD => Logic_1,
S => Partial_sum(i)
);
end generate adding_weights_input;

adding_partial_sums : for i in 0 to 5 generate
second_level : add_sub
port map (
A => Partial_sum(2*i),
B => Partial_sum(2*i+1),
C_IN => Logic_0,
C_OUT => OPEN,
ADD => Logic_1,
S => Partial_sum(i+12)
);
end generate adding_partial_sums;

adding_partial2_sums : for i in 0 to 2 generate
third_level : add_sub
port map (
A => Partial_sum(2*i+12),
B => Partial_sum((2*i+12)+1),
C_IN => Logic_0,
C_OUT => OPEN,
ADD => Logic_1,
S => Partial_sum(i+18)
);
end generate adding_partial2_sums;

Fourth_level : add_sub
port map(
A => Partial_sum(18),
B => Partial_sum(19),
C_IN => Logic_0,
C_OUT => OPEN,
ADD => Logic_1,
S => Partial_sum(21)
);

Fourth_level_zeros : add_sub
port map(
A => Partial_sum(20),
B => (others => '0'),
C_IN => Logic_0,
C_OUT => OPEN,
ADD => Logic_1,
S => Partial_sum(22)
);

Last_level : add_sub
port map(
A => Partial_sum(21),
B => Partial_sum(22),
C_IN => Logic_0,
C_OUT => OPEN,
ADD => Logic_1,
S => Partial_sum(23)
);

S <= Partial_sum(23);

end Behavioral;

where inhibitory_weights_array is defined in the package
type_definitions as:

TYPE inhibitory_weights_array IS array(0 to 23) of std_logic_vector(15
downto 0);

the component add_sub was generated by coregen and is in fact an
add/sub 16 bits with carry in, carry out.

Synthesis do not show any error, so I assume the VHDL is correct, but
when I try to check his behavioral simulation, the testbench tool fails
to create the right waveform, making port A as
an array of 24 elements of bit (equivalent to std_logic_vector(23
downto 0)) this can be seen below in the testbench text where A is
defined as:

A : In inhibitory_weights_arrayBase (0 To 23);

The full testbench file is the following:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library UNISIM;
use UNISIM.VComponents.all;
library work;
use work.type_definitions.all;
USE IEEE.STD_LOGIC_TEXTIO.ALL;
USE STD.TEXTIO.ALL;

ENTITY test_weight_Adder IS
END test_weight_Adder;

ARCHITECTURE testbench_arch OF test_weight_Adder IS
FILE RESULTS: TEXT OPEN WRITE_MODE IS "results.txt";

COMPONENT tree_adder
PORT (
A : In inhibitory_weights_arrayBase (0 To 23);
S : Out std_logic_vector (15 DownTo 0)
);
END COMPONENT;

SIGNAL A : inhibitory_weights_arrayBase (0 To 23) :=
"000000000000000000000000";
SIGNAL S : std_logic_vector (15 DownTo 0) := "0000000000000000";

SHARED VARIABLE TX_ERROR : INTEGER := 0;
SHARED VARIABLE TX_OUT : LINE;

BEGIN
UUT : tree_adder
PORT MAP (
A => A,
S => S
);

PROCESS
PROCEDURE CHECK_S(
next_S : std_logic_vector (15 DownTo 0);
TX_TIME : INTEGER
) IS
VARIABLE TX_STR : String(1 to 4096);
VARIABLE TX_LOC : LINE;
BEGIN
IF (S /= next_S) THEN
STD.TEXTIO.write(TX_LOC, string'("Error at
time="));
STD.TEXTIO.write(TX_LOC, TX_TIME);
STD.TEXTIO.write(TX_LOC, string'("ns S="));
IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, S);
STD.TEXTIO.write(TX_LOC, string'(", Expected = "));
IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_S);
STD.TEXTIO.write(TX_LOC, string'(" "));
TX_STR(TX_LOC.all'range) := TX_LOC.all;
STD.TEXTIO.writeline(RESULTS, TX_LOC);
STD.TEXTIO.Deallocate(TX_LOC);
ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
TX_ERROR := TX_ERROR + 1;
END IF;
END;
BEGIN
-- ------------- Current Time: 1000ns
WAIT FOR 1000 ns;
A <= "000000000000000000000000";

IF (TX_ERROR = 0) THEN
STD.TEXTIO.write(TX_OUT, string'("No errors or
warnings"));
STD.TEXTIO.writeline(RESULTS, TX_OUT);
ASSERT (FALSE) REPORT
"Simulation successful (not a failure). No
problems detected."
SEVERITY FAILURE;
ELSE
STD.TEXTIO.write(TX_OUT, TX_ERROR);
STD.TEXTIO.write(TX_OUT,
string'(" errors found in simulation"));
STD.TEXTIO.writeline(RESULTS, TX_OUT);
ASSERT (FALSE) REPORT "Errors found during
simulation"
SEVERITY FAILURE;
END IF;
END PROCESS;

END testbench_arch;


I have tried several options, for example I changed the entity to:

entity tree_adder is
port (
B0 : in std_logic_vector(15 downto 0);
B1 : in std_logic_vector(15 downto 0);
. . .
.
. . .
.
. . .
.
B23 : in std_logic_vector(15 downto 0);
S : out std_logic_vector(15 downto 0)
);
end tree_adder;

and then defining a signal (after architecture)

signal A : inhibitory_weights_array;

begin
A(0) <= B0;

and so on.

And it didn't work either, it seems ISE has problems dealing with
multidimensional arrays. So ISE is unable to create he right testbench
file to my entity, as a consequence, it is impossible to run a
simulation or even find a bug in the program.

Another problem came when I tried to create the RTL schematic, for the
entity, well I was able to get the right schematic, I mean a box with
24 inputs, all of them std_logic_vector(15 downto 0), which is correct,
but when I double-click on the RTL to see its internal structure a
pop-up window shows up saying "Xilinx - ISE has encountered a problem
and needs to close. We are sorry for the inconvenience." , just after
clicking the <CLOSE> button, it closes ISE and the project, not just
the pop-up window, so I have to restart ISE. So not even is possible to
check the internal structure of the entity to check if internal
connections are ok, which would give an idea of the correctness of the
program.

I am using ISE 8.1 and both ISE Simulator and Modelsim SE 5.8.

Any help will be greatly appreciated.
Regards,

Ruben
Click to expand...
 
On 13 Nov, 15:55, "Derek Simmons" <dereks...@gmail.com> wrote:
Keep in mind you are porting an algorithm that was original writen in a
programming language to a hardware description language, instead of
thinking of 'passing' you should be thinking of 'connecting' or
'sharing'. Instead of doing what you are trying to do why not store the
values in a chunk of memory and connect the address and data bus to
your component.
Click to expand...
Hello Derek,

Thanks for your answer. Actually, connecting a memory to the input of
the entity is a higher level program, this is just a sub-module of
another VHDL program, so following your advice, I am going to test the
VHDL program with the memory connected to the component "weight_adder"
and see what happens. However, I usually test all sub-modules before
testing the top module so I can get rid of possible bugs in any of the
sub-modules, which is what I wanted to do here. I still think there is
something wrong with the ISE dealing with this kind of multidimensional
arrays, because even when I change the port to individual
std_logic_vector(15 downto 0) inputs, and use an internal signal as
multidimensional array the simulation cannot be carried out for the
same reason.

Kind regards,

Ruben
 
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