Turning off Std checking in simulation

A

ALuPin@web.de

Guest
Hi newsgroup,

the following warning at intialization of a simulation

# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic
operand, the result will be 'X'(es).
# Time: 0 ns Iteration: 1 Instance: /cordic_tb/uut/add3

can be avoided by turning off the Std checking in the .do script when
using Modelsim:

set StdArithNoWarnings 1
run 1 ns;
set StdArithNoWarnings 0
run 10 ms;

Does somebody know wheter this technique is available in ActiveHDL ?
I could not find similar
set commands.


Thanks and Rgds
ALuPin
 
ALuPin@web.de wrote:
Hi newsgroup,

the following warning at intialization of a simulation

# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic
operand, the result will be 'X'(es).
# Time: 0 ns Iteration: 1 Instance: /cordic_tb/uut/add3

can be avoided by turning off the Std checking in the .do script when
using Modelsim:

set StdArithNoWarnings 1
run 1 ns;
set StdArithNoWarnings 0
run 10 ms;

Does somebody know wheter this technique is available in ActiveHDL ?
I could not find similar
set commands.


Thanks and Rgds
ALuPin
Click to expand...
There seems to be an argument to asim

-ieee_nowarn

regards
Alan

--
Alan Fitch
Doulos
http://www.doulos.com
 
On Jan 16, 4:32 am, "ALu...@web.de" <ALu...@web.de> wrote:
Hi newsgroup,

the following warning at intialization of a simulation

      # ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic
operand, the result will be 'X'(es).
      #    Time: 0 ns  Iteration: 1  Instance: /cordic_tb/uut/add3

can be avoided by turning off the Std checking in the  .do script when
using Modelsim:

      set StdArithNoWarnings 1
      run 1 ns;
      set StdArithNoWarnings 0
      run 10 ms;

Does somebody know wheter this technique is available in ActiveHDL ?
I could not find similar
set commands.

Thanks and Rgds
ALuPin
Click to expand...
To supress ieee warnings you can either use -ieee_nowarn switch with
asim command, or select something like 'Do not display IEEE warnings'
in Design->Design Settings->Simulation->VHDL
 
ALuPin@web.de wrote:
Hi newsgroup,

the following warning at intialization of a simulation

# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic
operand, the result will be 'X'(es).
# Time: 0 ns Iteration: 1 Instance: /cordic_tb/uut/add3

can be avoided by turning off the Std checking in the .do script when
using Modelsim:

set StdArithNoWarnings 1
run 1 ns;
set StdArithNoWarnings 0
run 10 ms;

Does somebody know wheter this technique is available in ActiveHDL ?
I could not find similar
set commands.
Click to expand...
In the VHDL-2008 release there is a package generic to shut these off.
 
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