T
Tom Torfs
Guest
Hello everyone,
I was wondering what the standard design practice is for turning off
the clock for some parts of an FPGA design while keeping other parts
running. I would assume simply gating the clock (followed by a global
clock buffer) introduces unacceptable amounts of clock skew. Perhaps
this method could be combined with use of a delay-locked loop as
present in the Xilinx FPGAs to keep the gated clock synchronous to the
rest of the system? Of course the gating circuit would also have to
take care of switching the gated clock glitchless, for which perhaps a
circuit could be used such as the one on
http://www.eedesign.com/features/exclusive/OEG20030626S0035 (referred
to by FAQ answer "Switching clocks without glitches"). Or am I
overlooking a simpler solution?
A similar problem exists when instead of turning the clock off it is
switched to a divided version (produced by counter) of itself, while
other parts keep running at the full speed or a different division
factor.
I would prefer to keep the whole system synchronous (e.g. all switched
or divided versions of the same clock with minimal skew) because else
the different parts would need anti-metastability sychronizers such as
2 or 3 flipflops in series on all their communication lines...
greetings,
Tom
I was wondering what the standard design practice is for turning off
the clock for some parts of an FPGA design while keeping other parts
running. I would assume simply gating the clock (followed by a global
clock buffer) introduces unacceptable amounts of clock skew. Perhaps
this method could be combined with use of a delay-locked loop as
present in the Xilinx FPGAs to keep the gated clock synchronous to the
rest of the system? Of course the gating circuit would also have to
take care of switching the gated clock glitchless, for which perhaps a
circuit could be used such as the one on
http://www.eedesign.com/features/exclusive/OEG20030626S0035 (referred
to by FAQ answer "Switching clocks without glitches"). Or am I
overlooking a simpler solution?
A similar problem exists when instead of turning the clock off it is
switched to a divided version (produced by counter) of itself, while
other parts keep running at the full speed or a different division
factor.
I would prefer to keep the whole system synchronous (e.g. all switched
or divided versions of the same clock with minimal skew) because else
the different parts would need anti-metastability sychronizers such as
2 or 3 flipflops in series on all their communication lines...
greetings,
Tom