ttl library ?

[Michael Schmid]

I started to write a ttl library but its really hard work.
Are there any good ones out there?
(without after, as they should synticise)

 

[Allan Herriman]

On Tue, 21 Dec 2004 11:32:43 +0100, Michael Schmid
<swimpy_pinball@yahoo.comSPAM> wrote:

I started to write a ttl library but its really hard work.
Are there any good ones out there?
(without after, as they should synticise)

Free Model Foundation.

http://www.eda.org/fmf/wwwpages/


Regards,
Allan

 

[Allan Herriman]

On Tue, 21 Dec 2004 21:47:23 +1100, Allan Herriman
<allan.herriman.hates.spam@ctam.com.au.invalid> wrote:

On Tue, 21 Dec 2004 11:32:43 +0100, Michael Schmid
swimpy_pinball@yahoo.comSPAM> wrote:

I started to write a ttl library but its really hard work.
Are there any good ones out there?

Oops, missed this bit:

(without after, as they should synticise)

1. The FMF libraries are simulation libraries. You can strip out the
vital stuff if you want.

2. 'after' does not cause problems with (most) synthesisers. They
simply ignore it.

3. Why do you want to synthesise TTL models? Are you performing a
(naive) conversion of an old schematic to VHDL? Do you understand why
this is fraught with difficulties?

Regards,
Allan

 

[Jonathan Bromley]

On Tue, 21 Dec 2004 11:32:43 +0100, Michael Schmid
<swimpy_pinball@yahoo.comSPAM> wrote:

I started to write a ttl library but its really hard work.
Are there any good ones out there?
(without after, as they should synticise)

Sounds easy but exceedingly tedious, to me.

Why bother? What's the point? Just do the parts that
you need for your legacy netlist.

The easy stuff (combinational gates with small numbers
of inputs) maps directly on to VHDL operators and
expressions.

More complicated combinational functions, such as
parity generators and special decoders, can easily
be re-coded as VHDL functions, which makes them a whole
lot more flexible and easier to use than they would be
if you packaged them as components.

Most of the synchronous blocks, such as the neat
multiplexer/flipflop combinations (74xx239???), are
just a pale shadow of stuff that you would want to
code in a VHDL clocked process; packaging them as
components will horribly distort your synthesisable
coding style.

Buffers and other bus-interface blocks such as
'245, '543 are unlikely to fit well with FPGA/ASIC
design methodologies because they use multi-drop
interconnect (to reduce package pin count) and
latches (to save logic). Steer clear of these, and
use a more appropriate interconnect scheme.

I have a cartload of 74F devices in my workshop.
It's hard persuading myself that I should get rid
of them, but I'm perfectly sure that I will
never use them again. My guess is that you are a
lot younger than I am; your sentimental attachment
to TTL logic should be much weaker than mine.

Enjoy the 21st century!!!
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL, Verilog, SystemC, Perl, Tcl/Tk, Verification, Project Services

Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, BH24 1AW, UK
Tel: +44 (0)1425 471223 mail:jonathan.bromley@doulos.com
Fax: +44 (0)1425 471573 Web: http://www.doulos.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

 

[Michael Schmid]

Allan Herriman schrieb:

On Tue, 21 Dec 2004 21:47:23 +1100, Allan Herriman
allan.herriman.hates.spam@ctam.com.au.invalid> wrote:


On Tue, 21 Dec 2004 11:32:43 +0100, Michael Schmid
swimpy_pinball@yahoo.comSPAM> wrote:


I started to write a ttl library but its really hard work.
Are there any good ones out there?


Oops, missed this bit:


(without after, as they should synticise)


1. The FMF libraries are simulation libraries. You can strip out the
vital stuff if you want.

2. 'after' does not cause problems with (most) synthesisers. They
simply ignore it.

3. Why do you want to synthesise TTL models? Are you performing a
(naive) conversion of an old schematic to VHDL? Do you understand why
this is fraught with difficulties?

Regards,
Allan

Thanks for the link, i already passed there once, but thought it's to
complicated ...

I am not sure, if it's not stupid anway. I have got a shematic from 1980
and would like to describe it as exactly as possible with vhdl.
I guess i'll do some "simple versions" of the archtiectures later on
too. But it's fun.

 

[FMF]

The FMF libraries are non-synthesizable but still may be usefull. You
can use them to simulate the original design so you have a way to know
thatn your "new" design is a complete match.


Michael Schmid wrote:

Allan Herriman schrieb:

On Tue, 21 Dec 2004 21:47:23 +1100, Allan Herriman
allan.herriman.hates.spam@ctam.com.au.invalid> wrote:


On Tue, 21 Dec 2004 11:32:43 +0100, Michael Schmid
swimpy_pinball@yahoo.comSPAM> wrote:


I started to write a ttl library but its really hard work.
Are there any good ones out there?



Oops, missed this bit:


(without after, as they should synticise)



1. The FMF libraries are simulation libraries. You can strip out the
vital stuff if you want.

2. 'after' does not cause problems with (most) synthesisers. They
simply ignore it.

3. Why do you want to synthesise TTL models? Are you performing a
(naive) conversion of an old schematic to VHDL? Do you understand why
this is fraught with difficulties?

Regards,
Allan


Thanks for the link, i already passed there once, but thought it's to
complicated ...

I am not sure, if it's not stupid anway. I have got a shematic from 1980
and would like to describe it as exactly as possible with vhdl.
I guess i'll do some "simple versions" of the archtiectures later on
too. But it's fun.