Trying to bias a JFET...

D

Dave

Guest
and wondering, if I am trying to put the gate at Vp or close thereto, is the
voltage applied in referrence to the source voltage or ground? I am
seriously considering putting the gate at ground potential with a current
limiting resistor on the source and using that to make the source positive
in referrence to the gate. Just not sure how much voltage to drop at that
point. If this is all gibberish please forgive, I am new to JFETs, and
biasing transistors in general. Was using a voltage divider for biasing,
but have not had much success at that. Trying once more before giving up
and going to the method described above. ANY input is much appreciated...

Dave
 
"Dave"
and wondering, if I am trying to put the gate at Vp or close thereto, is
the voltage applied in referrence to the source voltage or ground? I am
seriously considering putting the gate at ground potential with a current
limiting resistor on the source and using that to make the source positive
in referrence to the gate. Just not sure how much voltage to drop at that
point. If this is all gibberish please forgive, I am new to JFETs, and
biasing transistors in general. Was using a voltage divider for biasing,
but have not had much success at that. Trying once more before giving up
and going to the method described above. ANY input is much appreciated...
Click to expand...

** No possible until you post the number of the jfet.



..... Phil
 
On Sat, 21 Nov 2009 21:50:25 -0600, Dave wrote:

and wondering, if I am trying to put the gate at Vp or close thereto, is
the voltage applied in referrence to the source voltage or ground? I am
seriously considering putting the gate at ground potential with a
current limiting resistor on the source and using that to make the
source positive in referrence to the gate. Just not sure how much
voltage to drop at that point. If this is all gibberish please forgive,
I am new to JFETs, and biasing transistors in general. Was using a
voltage divider for biasing, but have not had much success at that.
Trying once more before giving up and going to the method described
above. ANY input is much appreciated...

Dave
Click to expand...
_Most_ of the JFET circuits that I have seen hold the gate at DC ground
and use a source resistor -- but as Phil says, the specific FET and what
you're trying to do with it make all the difference in the world.

--
www.wescottdesign.com
 
"Tim Wescott"
Dave wrote:
and wondering, if I am trying to put the gate at Vp or close thereto, is
the voltage applied in referrence to the source voltage or ground? I am
seriously considering putting the gate at ground potential with a
current limiting resistor on the source and using that to make the
source positive in referrence to the gate. Just not sure how much
voltage to drop at that point. If this is all gibberish please forgive,
I am new to JFETs, and biasing transistors in general. Was using a
voltage divider for biasing, but have not had much success at that.
Trying once more before giving up and going to the method described
above. ANY input is much appreciated...


_Most_ of the JFET circuits that I have seen hold the gate at DC ground
and use a source resistor -- but as Phil says, the specific FET and what
you're trying to do with it make all the difference in the world.
Click to expand...

** The OP wants to bias the JFET to " Vp " - which is a term meaning
"pinch off".

So a suitable source bias resistor to ground will likely have a very large
value - which makes for an near useless circuit.


...... Phil
 
Dave wrote:
and wondering, if I am trying to put the gate at Vp or close
thereto,
is the voltage applied in referrence to the source voltage or
ground?
I am seriously considering putting the gate at ground potential
with
a current limiting resistor on the source and using that to
make the
source positive in referrence to the gate. Just not sure how
much
voltage to drop at that point. If this is all gibberish please
forgive, I am new to JFETs, and biasing transistors in general.
Was
using a voltage divider for biasing, but have not had much
success at
that. Trying once more before giving up and going to the
method
described above. ANY input is much appreciated...
As others have indicated, it's not possible to give precise
Click to expand...
instructions without knowing the characteristics of the
particular JFET type you're using. However, some clarification is
possible:

1. The Vp is given with respect to the source, not ground.

2. Keeping the gate at ground potential and inserting a resistor
between source and ground is a common and convenient method of
biasing a JFET. It's even self-regulating. The source-drain
current produces a voltage drop across the source resistor,
making the source positive with respect to ground. Since the gate
is at ground potential, it will be negative with respect to the
source.

BUT that's praticable only if the transistor is to be biased in
the active region, not at pinch off. At pinch-off, there's little
current flowing through the source (zero in an ideal device), so
the source resistor will have to be of very high value to produce
the required voltage drop. Whether such a high resistance in
series with the source will present a problem depends on what the
circuit is intended to do.

3. The transistor can be biased at pinch off by providing either
a negative voltage to the gate or a positive voltage to the
source. But that bias voltage has to be adjustable because
transistors have wide tolerances with most of their
characteristics, including the Vp, and then there's the effect of
temperature variations.
 
"pimpom" <pimpom@invalid.com> wrote in message
news:heatod$9j4$1@news.albasani.net...
Dave wrote:
and wondering, if I am trying to put the gate at Vp or close thereto,
is the voltage applied in referrence to the source voltage or ground?
I am seriously considering putting the gate at ground potential with
a current limiting resistor on the source and using that to make the
source positive in referrence to the gate. Just not sure how much
voltage to drop at that point. If this is all gibberish please
forgive, I am new to JFETs, and biasing transistors in general. Was
using a voltage divider for biasing, but have not had much success at
that. Trying once more before giving up and going to the method
described above. ANY input is much appreciated...
As others have indicated, it's not possible to give precise instructions
without knowing the characteristics of the particular JFET type you're
using. However, some clarification is possible:

1. The Vp is given with respect to the source, not ground.

2. Keeping the gate at ground potential and inserting a resistor between
source and ground is a common and convenient method of biasing a JFET.
It's even self-regulating. The source-drain current produces a voltage
drop across the source resistor, making the source positive with respect
to ground. Since the gate is at ground potential, it will be negative with
respect to the source.

BUT that's praticable only if the transistor is to be biased in the active
region, not at pinch off. At pinch-off, there's little current flowing
through the source (zero in an ideal device), so the source resistor will
have to be of very high value to produce the required voltage drop.
Whether such a high resistance in series with the source will present a
problem depends on what the circuit is intended to do.

3. The transistor can be biased at pinch off by providing either a
negative voltage to the gate or a positive voltage to the source. But that
bias voltage has to be adjustable because transistors have wide tolerances
with most of their characteristics, including the Vp, and then there's the
effect of temperature variations.
Click to expand...
Thanks, all for the feedback. And thank you, pimpom, for the extra. The
JFET in question is an NTE451, and I am wanting to bias it in the active
region, not at pinchoff (I now realize). It is intended as a small-signal
amplifier, in the front end of a "hearing aid" for my shortwave radio. And
I am intending to bypass the source resistor with a .01 uF cap. (Please see
complete schematic posted to abse. It is still set up using VDB.)

Last night I dug out my copy of Les Hayward's Intro to RF Design, and think
I was actually able to follow it. Last time I looked at it it was beyond
me, but after finding his into to JFET biasing on the 'net, and worked
through those equations, it now seems easy. Am now thinking I need a 820
ohm source resistor and a 1K ohm resistor on the drain, with the gate
biased between a 1.8 M and a 3.6 M resistor going from ground to +12V. (Or
is this more gibberish?)

Again, please forgive any nonsense, I am trying to learn how all this
works...

Thanks much,

Dave
 
"Dave" <db5151@hotmail.com> wrote in message
news:OvednaiuGZzAxpTWnZ2dnUVZ_hudnZ2d@posted.internetamerica...
"pimpom" <pimpom@invalid.com> wrote in message
news:heatod$9j4$1@news.albasani.net...
Dave wrote:
and wondering, if I am trying to put the gate at Vp or close thereto,
is the voltage applied in referrence to the source voltage or ground?
I am seriously considering putting the gate at ground potential with
a current limiting resistor on the source and using that to make the
source positive in referrence to the gate. Just not sure how much
voltage to drop at that point. If this is all gibberish please
forgive, I am new to JFETs, and biasing transistors in general. Was
using a voltage divider for biasing, but have not had much success at
that. Trying once more before giving up and going to the method
described above. ANY input is much appreciated...
As others have indicated, it's not possible to give precise instructions
without knowing the characteristics of the particular JFET type you're
using. However, some clarification is possible:

1. The Vp is given with respect to the source, not ground.

2. Keeping the gate at ground potential and inserting a resistor between
source and ground is a common and convenient method of biasing a JFET.
It's even self-regulating. The source-drain current produces a voltage
drop across the source resistor, making the source positive with respect
to ground. Since the gate is at ground potential, it will be negative
with respect to the source.

BUT that's praticable only if the transistor is to be biased in the
active region, not at pinch off. At pinch-off, there's little current
flowing through the source (zero in an ideal device), so the source
resistor will have to be of very high value to produce the required
voltage drop. Whether such a high resistance in series with the source
will present a problem depends on what the circuit is intended to do.

3. The transistor can be biased at pinch off by providing either a
negative voltage to the gate or a positive voltage to the source. But
that bias voltage has to be adjustable because transistors have wide
tolerances with most of their characteristics, including the Vp, and then
there's the effect of temperature variations.


Thanks, all for the feedback. And thank you, pimpom, for the extra. The
JFET in question is an NTE451, and I am wanting to bias it in the active
region, not at pinchoff (I now realize). It is intended as a small-signal
amplifier, in the front end of a "hearing aid" for my shortwave radio.
And I am intending to bypass the source resistor with a .01 uF cap.
(Please see complete schematic posted to abse. It is still set up using
VDB.)

Last night I dug out my copy of Les Hayward's Intro to RF Design, and
think I was actually able to follow it. Last time I looked at it it was
beyond me, but after finding his into to JFET biasing on the 'net, and
worked through those equations, it now seems easy. Am now thinking I
need a 820 ohm source resistor and a 1K ohm resistor on the drain, with
the gate biased between a 1.8 M and a 3.6 M resistor going from ground to
+12V. (Or is this more gibberish?)

Again, please forgive any nonsense, I am trying to learn how all this
works...

Thanks much,

Dave
Click to expand...
Argh. Just realized what I wrote doesn't match what I posed in abse. It
shows a 620 ohm source resistor and an 820 ohm resistor on the drain.
Apologies. This is why I shouldn't post when I am half asleep. Anyway, you
get the idea. This is basically what I am working with, although I am
probably going to eventually do it with one less JFET.

Thanks again for any cussin' / discussion.

Dave
 
On Sun, 22 Nov 2009 09:40:17 -0600, "Dave" <db5151@hotmail.com> wrote:

"pimpom" <pimpom@invalid.com> wrote in message
news:heatod$9j4$1@news.albasani.net...
Dave wrote:
and wondering, if I am trying to put the gate at Vp or close thereto,
is the voltage applied in referrence to the source voltage or ground?
I am seriously considering putting the gate at ground potential with
a current limiting resistor on the source and using that to make the
source positive in referrence to the gate. Just not sure how much
voltage to drop at that point. If this is all gibberish please
forgive, I am new to JFETs, and biasing transistors in general. Was
using a voltage divider for biasing, but have not had much success at
that. Trying once more before giving up and going to the method
described above. ANY input is much appreciated...
As others have indicated, it's not possible to give precise instructions
without knowing the characteristics of the particular JFET type you're
using. However, some clarification is possible:

1. The Vp is given with respect to the source, not ground.

2. Keeping the gate at ground potential and inserting a resistor between
source and ground is a common and convenient method of biasing a JFET.
It's even self-regulating. The source-drain current produces a voltage
drop across the source resistor, making the source positive with respect
to ground. Since the gate is at ground potential, it will be negative with
respect to the source.

BUT that's praticable only if the transistor is to be biased in the active
region, not at pinch off. At pinch-off, there's little current flowing
through the source (zero in an ideal device), so the source resistor will
have to be of very high value to produce the required voltage drop.
Whether such a high resistance in series with the source will present a
problem depends on what the circuit is intended to do.

3. The transistor can be biased at pinch off by providing either a
negative voltage to the gate or a positive voltage to the source. But that
bias voltage has to be adjustable because transistors have wide tolerances
with most of their characteristics, including the Vp, and then there's the
effect of temperature variations.


Thanks, all for the feedback. And thank you, pimpom, for the extra. The
JFET in question is an NTE451, and I am wanting to bias it in the active
region, not at pinchoff (I now realize). It is intended as a small-signal
amplifier, in the front end of a "hearing aid" for my shortwave radio. And
I am intending to bypass the source resistor with a .01 uF cap. (Please see
complete schematic posted to abse. It is still set up using VDB.)

Last night I dug out my copy of Les Hayward's Intro to RF Design, and think
I was actually able to follow it. Last time I looked at it it was beyond
me, but after finding his into to JFET biasing on the 'net, and worked
through those equations, it now seems easy. Am now thinking I need a 820
ohm source resistor and a 1K ohm resistor on the drain, with the gate
biased between a 1.8 M and a 3.6 M resistor going from ground to +12V. (Or
is this more gibberish?)

Again, please forgive any nonsense, I am trying to learn how all this
works...

Thanks much,

Dave
Click to expand...
You will probably get little, or likely no, net gain from a jfet used
as a wideband amplifier like this. If your shortwave looks like a 50
ohm load, and the jfet has a transconductance of 20 mS - high for a
typical jfet - the voltage gain is one.

A jfet will make useful RF gain if you tune its input and output to
match the circuit impedances, which can be a nuisance.

GaAs MMICS are cheap and really easy to use and do provide bunches of
wideband gain in 50 ohm systems.

Things like this:

http://www.minicircuits.com/pdfs/ERA-5+.pdf

John
 
On Nov 22, 7:40 am, "Dave" <db5...@hotmail.com> wrote:
JFET in question is an NTE451, and I am wanting to bias it in the active
region, not at pinchoff (I now realize).  It is intended as a small-signal
amplifier, in the front end of a "hearing aid" for my shortwave radio.
Click to expand...
Two beneficial aspects of a front-end RF amp are that it isolates the
antenna from (for instance) your LO oscillator, and that it matches
the
antenna impedance to a random input impedance.

Unless it has lower noise than the shortwave radio input circuit, it
won't give much benefit, IMHO. There's probably good gain-control
circuitry in the RF and/or IF amplifiers already, and perhaps a
tracking
RF filter (which connects with the tuning knob, isn't easy to do in
an outboard amplifier section).

In terms of matching to the antenna, a grounded-gate configuration
with the source fed from a bias current source can have low-ish input
impedance, and gives good in/out isolation.
 
"Dave" <db5151@hotmail.com> wrote in message news:Za-dnQ4QVKxnKZXWnZ2dnUVZ_g-dnZ2d@posted.internetamerica...
and wondering, if I am trying to put the gate at Vp or close thereto, is the
voltage applied in referrence to the source voltage or ground? I am
seriously considering putting the gate at ground potential with a current
limiting resistor on the source and using that to make the source positive
in referrence to the gate. Just not sure how much voltage to drop at that
point. If this is all gibberish please forgive, I am new to JFETs, and
biasing transistors in general. Was using a voltage divider for biasing,
but have not had much success at that. Trying once more before giving up
and going to the method described above. ANY input is much appreciated...

Dave
Click to expand...
 
You must log in or register to reply here.

Welcome to EDABoard.com

Sponsor

Back
Top