Truncate with fixed_pkg

A

Alfreeeeed

Guest
I have been using fixed_pkg vhdl package and works fine for me
but..........as I use the resize function a lot for math operations, a
rounding routine is implemented synthesizing a lot of logic I wouldnt
need to use if I only truncate the result. I know truncate can be
implemented by modifying generics or constants but I couldnt figure
out HOW.

Is my point clear enough? If so, can you help me?

sorry for my not-so-good english.


Alfredo
 
On Sep 24, 8:09 am, Alfreeeeed <Alfredo.Tad...@gmail.com> wrote:
I have been using fixed_pkg vhdl package and works fine for me
but..........as I use the resize function a lot for math operations, a
rounding routine is implemented synthesizing a lot of logic I wouldnt
need to use if I only truncate the result. I know truncate can be
implemented  by modifying generics or constants but I couldnt figure
out HOW.

Is my point clear enough? If so, can you help me?

sorry for my not-so-good english.

Alfredo
Click to expand...
Refer to page 4 of the user's guide (Fixed_ug.pdf) for more info.

In short, the resize function has an argument for the rounding style,
if you don't specify a value for that argument it defaults to
'fixed_round'. There is also an argument for overflow style that
defaults to 'fixed_saturate'. You'll probably want to change both of
these. Modify your use of resize to be of the form

xyz <= resize(abc, xyz'left, xyz'right, fixed_wrap, fixed_truncate);

KJ
 
On Sep 24, 8:09 am, Alfreeeeed <Alfredo.Tad...@gmail.com> wrote:
I have been using fixed_pkg vhdl package and works fine for me
but..........as I use the resize function a lot for math operations, a
rounding routine is implemented synthesizing a lot of logic I wouldnt
need to use if I only truncate the result. I know truncate can be
implemented  by modifying generics or constants but I couldnt figure
out HOW.

Is my point clear enough? If so, can you help me?

sorry for my not-so-good english.

Alfredo
Click to expand...
Refer to page 4 of the user's guide (Fixed_ug.pdf) for more info.

Basically the resize function has a parameter for controlling how
rounding is performed that if you don't specify it, defaults to the
rounding style that causes the additional synthesized logic. It also
has a parameter for controlling overflow that you may want to specify
as well since it defaults to 'saturate' style which will consume more
logic as well instead of wrapping. Refer to the user's guide about
some of the considerations you should make but basically you'll need
to change your use of resize from this...

xyz <= resize(abc, xyz'left, xyz'right);

to this...

xyz <= resize(abc, xyz'left, xyz'right,fixed_truncate, fixed_wrap);

KJ
 
On Sep 24, 11:10 am, KJ <kkjenni...@sbcglobal.net> wrote:
On Sep 24, 8:09 am, Alfreeeeed <Alfredo.Tad...@gmail.com> wrote:

I have been using fixed_pkg vhdl package and works fine for me
but..........as I use the resize function a lot for math operations, a
rounding routine is implemented synthesizing a lot of logic I wouldnt
need to use if I only truncate the result. I know truncate can be
implemented  by modifying generics or constants but I couldnt figure
out HOW.

Is my point clear enough? If so, can you help me?

sorry for my not-so-good english.

Alfredo

Refer to page 4 of the user's guide (Fixed_ug.pdf) for more info.

Basically the resize function has a parameter for controlling how
rounding is performed that if you don't specify it, defaults to the
rounding style that causes the additional synthesized logic.  It also
has a parameter for controlling overflow that you may want to specify
as well since it defaults to 'saturate' style which will consume more
logic as well instead of wrapping.  Refer to the user's guide about
some of the considerations you should make but basically you'll need
to change your use of resize from this...

xyz <= resize(abc, xyz'left, xyz'right);

to this...

xyz <= resize(abc, xyz'left, xyz'right,fixed_truncate, fixed_wrap);

KJ
Click to expand...
KJ,what you suggested went really well. I even didn´t have to look for
the pdf.
Thanks a lot.
 
Alfreeeeed wrote:
On Sep 24, 11:10 am, KJ <kkjenni...@sbcglobal.net> wrote:
On Sep 24, 8:09 am, Alfreeeeed <Alfredo.Tad...@gmail.com> wrote:

I have been using fixed_pkg vhdl package and works fine for me
but..........as I use the resize function a lot for math operations, a
rounding routine is implemented synthesizing a lot of logic I wouldnt
need to use if I only truncate the result. I know truncate can be
implemented by modifying generics or constants but I couldnt figure
out HOW.
Is my point clear enough? If so, can you help me?
sorry for my not-so-good english.
Alfredo
Refer to page 4 of the user's guide (Fixed_ug.pdf) for more info.

Basically the resize function has a parameter for controlling how
rounding is performed that if you don't specify it, defaults to the
rounding style that causes the additional synthesized logic. It also
has a parameter for controlling overflow that you may want to specify
as well since it defaults to 'saturate' style which will consume more
logic as well instead of wrapping. Refer to the user's guide about
some of the considerations you should make but basically you'll need
to change your use of resize from this...

xyz <= resize(abc, xyz'left, xyz'right);

to this...

xyz <= resize(abc, xyz'left, xyz'right,fixed_truncate, fixed_wrap);

KJ

KJ,what you suggested went really well. I even didn´t have to look for
the pdf.
Thanks a lot.
Click to expand...
Good to see people using these packages. Once I get off of the major
ASIC jobs I'm currently doing I'll be updating the web page. I've
created several things, including a version of the fixed point package
which don't automatically change the size of the results.
 
On Sat, 27 Sep 2008 22:33:55 -0400, David Bishop <dbishop@vhdl.org> wrote:

Good to see people using these packages. Once I get off of the major
ASIC jobs I'm currently doing I'll be updating the web page. I've
created several things, including a version of the fixed point package
which don't automatically change the size of the results.
Click to expand...
Is Xilinx synthesis 9.2 or 10.1 good enough to translate them?

I have a lot of DSP/filtering/demodulation algorithms that
I would like to prettify for publication and getting rid
of all that explicit scaling/rounding/saturating would be
a major step forward.

regards, Gerhard
 
On Sep 28, 1:24 pm, Gerhard Hoffmann <dk...@hoffmann-hochfrequenz.de>
wrote:
On Sat, 27 Sep 2008 22:33:55 -0400, David Bishop <dbis...@vhdl.org> wrote:
Good to see people using these packages.   Once I get off of the major
ASIC jobs I'm currently doing I'll be updating the web page.  I've
created several things, including a version of the fixed point package
which don't automatically change the size of the results.

Is Xilinx synthesis 9.2 or 10.1 good enough to translate them?

I have a lot of DSP/filtering/demodulation algorithms that
I would like to prettify for publication and getting rid
of all that explicit scaling/rounding/saturating would be
a major step forward.

regards, Gerhard
Click to expand...
David, thanks for this package. A lot of time has been saved
programming with it, specially for the Signal Processing algorithms. I
wish the new VHDL was out soon so we can take advantage of all its
features.

Regards

Alfredo
 
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