Trouble with text output

[Zac Bond]

I am constructing a 5-bit multiplier, and am having a great deal of
difficulty getting my outputs to display onscreen during my testbench.
I had *thought* that the following is correct:


architecture bit5_signed_multiplier_testbench_arch of
bit5_signed_multiplier_testbench is

component bit5_signed_multiplier
-- big irrelevent port list
end component;

signal t_multd, t_multr: unsigned(4 downto 0) := "00000";
signal t_go : std_logic := '0';
signal t_Z: unsigned(9 downto 0) := "0000000000";

begin
TestMult: bit5_signed_multiplier port map (t_multd, t_multr, t_go,
t_Z);

Tester: process
variable s: line;

begin
t_multd <= "01000"; -- multiplicand
t_multr <= "01000"; -- multiplier
wait for 5 ns;
t_go <= '1'; -- "start computation" signal
wait for 5 ns;

write(s, "Answer is Z = "); -- line 105
write(s, std_logic_vector(t_Z), right, 0); -- line 106
writeline(output, s);

t_go <= '0';
assert false report "Simulation complete." severity failure;
end process Tester;
end bit5_signed_multiplier_testbench_arch;


Unfortunately, when I compile I get the following messages:

ERROR: P4A.vhd(105): Subprogram "write" is ambiguous.
ERROR: P4A.vhd(105): type error resolving function call: write
ERROR: P4A.vhd(106): No feasible entries for subprogram write

I don't understand why there are no feasible write entries for a
std_logic_vector. What is the correct way to write these output
functions?

Thanks,
Zac Bond
zwb2@cwru.edu

 

[VhdlCohen]

I don't understand why there are no feasible write entries for a
std_logic_vector. What is the correct way to write these output
functions?

Use the image package that is at my site.
As a general recommendation, a user needs to know what's in a package.
That question was alos addressed quite often in newsgroups, and is in the VHDL
FAQ,\http://www.eda.org/comp.lang.vhdl/

----------------------------------------------------------------------------
Ben Cohen Publisher, Trainer, Consultant (310) 721-4830
http://www.vhdlcohen.com/ vhdlcohen@aol.com
Author of following textbooks:
* Using PSL/SUGAR with Verilog and VHDL
Guide to Property Specification Language for ABV, 2003 isbn 0-9705394-4-4
* Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn
0-9705394-2-8
* Component Design by Example ", 2001 isbn 0-9705394-0-1
* VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn 0-7923-8474-1
* VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn 0-7923-8115
------------------------------------------------------------------------------

 

[Jim Lewis]

This is a wierd VHDL issue.

write(s, "Answer is Z = "); -- line 105
Needs to be:

write(s, string'("Answer is Z = "));

Rule of Thumb: if it says ambiguous, not only
does the desired function exist, there are two or
more that can match. The type qualifier fixes this
issue by identifying exactly the one you need.

write(s, std_logic_vector(t_Z), right, 0); -- line 106
Make sure to include:

use ieee.std_logic_textio.all ;

If this does not work, look in the package
std_logic_textio and understand why you are
specifying a field width of 0 instead of:
write(s, std_logic_vector(t_Z));

Good Luck,
Jim
--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Jim Lewis
Director of Training mailto:Jim@SynthWorks.com
SynthWorks Design Inc. http://www.SynthWorks.com
1-503-590-4787

Expert VHDL Training for Hardware Design and Verification
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~


Zac Bond wrote:

I am constructing a 5-bit multiplier, and am having a great deal of
difficulty getting my outputs to display onscreen during my testbench.
I had *thought* that the following is correct:


architecture bit5_signed_multiplier_testbench_arch of
bit5_signed_multiplier_testbench is

component bit5_signed_multiplier
-- big irrelevent port list
end component;

signal t_multd, t_multr: unsigned(4 downto 0) := "00000";
signal t_go : std_logic := '0';
signal t_Z: unsigned(9 downto 0) := "0000000000";

begin
TestMult: bit5_signed_multiplier port map (t_multd, t_multr, t_go,
t_Z);

Tester: process
variable s: line;

begin
t_multd <= "01000"; -- multiplicand
t_multr <= "01000"; -- multiplier
wait for 5 ns;
t_go <= '1'; -- "start computation" signal
wait for 5 ns;

write(s, "Answer is Z = "); -- line 105
write(s, std_logic_vector(t_Z), right, 0); -- line 106
writeline(output, s);

t_go <= '0';
assert false report "Simulation complete." severity failure;
end process Tester;
end bit5_signed_multiplier_testbench_arch;


Unfortunately, when I compile I get the following messages:

ERROR: P4A.vhd(105): Subprogram "write" is ambiguous.
ERROR: P4A.vhd(105): type error resolving function call: write
ERROR: P4A.vhd(106): No feasible entries for subprogram write

I don't understand why there are no feasible write entries for a
std_logic_vector. What is the correct way to write these output
functions?

Thanks,
Zac Bond
zwb2@cwru.edu