Trouble with $readmemh in ModelSim

[Chris Carlen]

Hi:

I'm trying to use a memory in a Verilog testbench to generate arbitrary
waveforms to stimulate my Verilog module.

I'm using ModelSim XE II/Starter 5.7c with Xilinx Webpack 5.2i.

Modelsim complains with this message:

# Model Technology ModelSim XE II vlog 5.7c Compiler 2003.03 Mar 15 2003
# -- Compiling module testbench
# ** Error: E:/xilinx/CPLD-Magic-Box/cummins-camprox/testbench.tf(4):
near "$readmemh": syntax error
vlog -reportprogress 300 -work work
{E:/xilinx/CPLD-Magic-Box/cummins-camprox/testbench.tf}



The offending line of testbench code looks like this:

-------------------------------------------
module testbench();

reg [3:0] wave [0:191]; // create 192 x 4-bit waveform data table

$readmemh( "testhex.txt", wave ); // Load RAM from file

endmodule
-------------------------------------------

The text file looks like:

-------------------------------------------
4'h1 //count1(referringtothe74LS193datahere)
4'h1
4'h1
4'h1

4'h0
4'h0
4'h0
4'h0

4'h1 //count2
4'h1
// etc.
--------------------------------------------


Any clues?


Thanks.



--
____________________________________
Christopher R. Carlen
Principal Laser/Optical Technologist
Sandia National Laboratories CA USA
crcarle@sandia.gov

 

[Chris Carlen]

Duane Clark wrote:

Chris Carlen wrote:

module testbench();

reg [3:0] wave [0:191]; // create 192 x 4-bit waveform data table
initial
begin
$readmemh( "testhex.txt", wave ); // Load RAM from file
end
endmodule

Duh, of course! You can't assign to regs except inside initial/always

Thanks!


--
____________________________________
Christopher R. Carlen
Principal Laser/Optical Technologist
Sandia National Laboratories CA USA
crcarle@sandia.gov

 

[Kevin Neilson]

"Chris Carlen" <crcarle@BOGUS.sandia.gov> wrote in message
news:cbt2af01rlh@news3.newsguy.com...

Kevin Neilson wrote:
Chris,
The format of the text file has to be in hex bytes, like this:
ff // first byte
ff ff // second and third byte
aa bb cc // more bytes

You can't use the 4'hf notation of Verilog.
You can get more flexibility by using the Verilog 2001 I/O commands.
-Kevin


Thanks for the input.

Using the tip provided by Duane Clark, I have fixed the syntax error. I
simply needed to use an initial statement.

But while my compiler is no longer reporting a syntax error, I have yet
to run a sim and verify that the data is correctly read.

So I will have to confirm what you are saying later. But if you are
correct, then I will need this part of the picture too, so thanks!

Where can I learn about these Verilog 2001 IO commands? Are they
implemented in Modelsim? I have read the documentation a little bit.
I'll have to look in there some more.

Good day!

I don't know if you'll have luck finding help in the Modelsim documentation.

That will tell you what commands are implemented, but not how to use them.
I think the best bet may be to get out a C book and look up 'fscanf' and
'getc' and such. I think the Verilog commands are supposed to operate just
like the C ones. -Kevin