Trouble with $readmemh in ModelSim

C

Chris Carlen

Guest
Hi:

I'm trying to use a memory in a Verilog testbench to generate arbitrary
waveforms to stimulate my Verilog module.

I'm using ModelSim XE II/Starter 5.7c with Xilinx Webpack 5.2i.

Modelsim complains with this message:

# Model Technology ModelSim XE II vlog 5.7c Compiler 2003.03 Mar 15 2003
# -- Compiling module testbench
# ** Error: E:/xilinx/CPLD-Magic-Box/cummins-camprox/testbench.tf(4):
near "$readmemh": syntax error
vlog -reportprogress 300 -work work
{E:/xilinx/CPLD-Magic-Box/cummins-camprox/testbench.tf}



The offending line of testbench code looks like this:

-------------------------------------------
module testbench();

reg [3:0] wave [0:191]; // create 192 x 4-bit waveform data table

$readmemh( "testhex.txt", wave ); // Load RAM from file

endmodule
-------------------------------------------

The text file looks like:

-------------------------------------------
4'h1 //count1(referringtothe74LS193datahere)
4'h1
4'h1
4'h1

4'h0
4'h0
4'h0
4'h0

4'h1 //count2
4'h1
// etc.
--------------------------------------------


Any clues?


Thanks.



--
____________________________________
Christopher R. Carlen
Principal Laser/Optical Technologist
Sandia National Laboratories CA USA
crcarle@sandia.gov
 
Chris Carlen wrote:

module testbench();

reg [3:0] wave [0:191]; // create 192 x 4-bit waveform data table
initial
begin
$readmemh( "testhex.txt", wave ); // Load RAM from file
end
endmodule

--
My real email is akamail.com@dclark (or something like that).
 
"Chris Carlen" <crcarle@BOGUS.sandia.gov> wrote in message
news:cbsjei0nld@news2.newsguy.com...
Hi:

I'm trying to use a memory in a Verilog testbench to generate arbitrary
waveforms to stimulate my Verilog module.

I'm using ModelSim XE II/Starter 5.7c with Xilinx Webpack 5.2i.

Modelsim complains with this message:

# Model Technology ModelSim XE II vlog 5.7c Compiler 2003.03 Mar 15 2003
# -- Compiling module testbench
# ** Error: E:/xilinx/CPLD-Magic-Box/cummins-camprox/testbench.tf(4):
near "$readmemh": syntax error
vlog -reportprogress 300 -work work
{E:/xilinx/CPLD-Magic-Box/cummins-camprox/testbench.tf}



The offending line of testbench code looks like this:

-------------------------------------------
module testbench();

reg [3:0] wave [0:191]; // create 192 x 4-bit waveform data table

$readmemh( "testhex.txt", wave ); // Load RAM from file

endmodule
-------------------------------------------

The text file looks like:

-------------------------------------------
4'h1 //count1(referringtothe74LS193datahere)
4'h1
4'h1
4'h1

4'h0
4'h0
4'h0
4'h0

4'h1 //count2
4'h1
// etc.
--------------------------------------------


Any clues?


Thanks.

Chris,
Click to expand...
The format of the text file has to be in hex bytes, like this:
ff // first byte
ff ff // second and third byte
aa bb cc // more bytes

You can't use the 4'hf notation of Verilog.
You can get more flexibility by using the Verilog 2001 I/O commands.
-Kevin
 
I agree that the omission of the initial statement is the most likely
cause of the syntax error but the format of the file also needs to be
modified to avoid the next error so both follow-up posters are correct.
The original poster is using 5.2i so this may not help him but for the
benefit of those on the more recent version of ISE, version 6.2i, the
Language Templates were updated for that release and include a fairly
good example I wrote for this function if I must say so myself. For
those that want to see this, open up the 6.2i Language Templates and go
to: Verilog --> Simulation Constructs --> System Tasks and Functions -->
File I/O --> Read Memory. There you will find an info file that explain
how to use this as well as a template that includes the missing initial
statement:

INFO:

// Information on the $readmemb and $readmemh system functions
// ===========================================================
//
// $readmemb is a system function which will read binary data from a
// specified file. The syntax is the following:
// $readmemb ("<file_name>", <reg_name>); where the <file_name> is
// the name and location of the file containing the binary data and
// the <reg_name> is a 2-D register array in which the memory data
// is stored. The data file may only contain binary data, white
// spaces and comments. This function is generally executed within
// an initial block.
//
// $readmemh is the same as $readmemb with the exception that it
// inputs hex data as the read values.
//
// Example of reading binary data from a file:

reg [31:0] prom_data[1023:0];

initial
$readmemb("../data/mem_file.dat", prom_data);


Template for $readmemh:

reg [<memory_width>] <reg_name> [<memory_depth>];

initial
$readmemh ("<file_name>", <reg_name>);



I did not include a sample file as I did not think it would be necessary
but perhaps I should based on what I have seen here. I may add that as
a possible enhancement for a future release.

-- Brian
 
Duane Clark wrote:
Chris Carlen wrote:

module testbench();

reg [3:0] wave [0:191]; // create 192 x 4-bit waveform data table
initial
begin
$readmemh( "testhex.txt", wave ); // Load RAM from file
end
endmodule
Click to expand...

Duh, of course! You can't assign to regs except inside initial/always

Thanks!


--
____________________________________
Christopher R. Carlen
Principal Laser/Optical Technologist
Sandia National Laboratories CA USA
crcarle@sandia.gov
 
Kevin Neilson wrote:
Chris,
The format of the text file has to be in hex bytes, like this:
ff // first byte
ff ff // second and third byte
aa bb cc // more bytes

You can't use the 4'hf notation of Verilog.
You can get more flexibility by using the Verilog 2001 I/O commands.
-Kevin
Click to expand...

Thanks for the input.

Using the tip provided by Duane Clark, I have fixed the syntax error. I
simply needed to use an initial statement.

But while my compiler is no longer reporting a syntax error, I have yet
to run a sim and verify that the data is correctly read.

So I will have to confirm what you are saying later. But if you are
correct, then I will need this part of the picture too, so thanks!

Where can I learn about these Verilog 2001 IO commands? Are they
implemented in Modelsim? I have read the documentation a little bit.
I'll have to look in there some more.

Good day!



--
____________________________________
Christopher R. Carlen
Principal Laser/Optical Technologist
Sandia National Laboratories CA USA
crcarle@sandia.gov
 
On Tue, 29 Jun 2004 17:42:55 -0700, Chris Carlen
<crcarle@BOGUS.sandia.gov> wrote:

Where can I learn about these Verilog 2001 IO commands?
Click to expand...
The IEEE standard (of course); but there's also some useful
stuff on Stuart Sutherland's V2k1 web site
http://www.sutherland-hdl.com/Verilog-2001/

Are they implemented in Modelsim?
Click to expand...
AFAIK ModelSim implements all the new file I/O stuff. It
looks very much like the corresponding C functions
(getc, gets, fscanf, fseek, that sort of thing) but there
are many differences of detail, so proceed with caution.
Most of the yukky bits are inevitable because of the
bizarre way Verilog handles strings.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL, Verilog, SystemC, Perl, Tcl/Tk, Verification, Project Services

Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, BH24 1AW, UK
Tel: +44 (0)1425 471223 mail:jonathan.bromley@doulos.com
Fax: +44 (0)1425 471573 Web: http://www.doulos.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
 
"Chris Carlen" <crcarle@BOGUS.sandia.gov> wrote in message
news:cbt2af01rlh@news3.newsguy.com...
Kevin Neilson wrote:
Chris,
The format of the text file has to be in hex bytes, like this:
ff // first byte
ff ff // second and third byte
aa bb cc // more bytes

You can't use the 4'hf notation of Verilog.
You can get more flexibility by using the Verilog 2001 I/O commands.
-Kevin


Thanks for the input.

Using the tip provided by Duane Clark, I have fixed the syntax error. I
simply needed to use an initial statement.

But while my compiler is no longer reporting a syntax error, I have yet
to run a sim and verify that the data is correctly read.

So I will have to confirm what you are saying later. But if you are
correct, then I will need this part of the picture too, so thanks!

Where can I learn about these Verilog 2001 IO commands? Are they
implemented in Modelsim? I have read the documentation a little bit.
I'll have to look in there some more.

Good day!

I don't know if you'll have luck finding help in the Modelsim documentation.
Click to expand...
That will tell you what commands are implemented, but not how to use them.
I think the best bet may be to get out a C book and look up 'fscanf' and
'getc' and such. I think the Verilog commands are supposed to operate just
like the C ones. -Kevin
 
Kevin Neilson wrote:

"Chris Carlen" <crcarle@BOGUS.sandia.gov> wrote in message
news:cbt2af01rlh@news3.newsguy.com...

Where can I learn about these Verilog 2001 IO commands? Are they
implemented in Modelsim? I have read the documentation a little bit.
I'll have to look in there some more.

Good day!


I don't know if you'll have luck finding help in the Modelsim documentation.
That will tell you what commands are implemented, but not how to use them.
I think the best bet may be to get out a C book and look up 'fscanf' and
'getc' and such. I think the Verilog commands are supposed to operate just
like the C ones. -Kevin
Click to expand...

If all you are planning to do is read in binary or hex data from an
external file, I find the $readmemb and $readmemh command much easier to
use. Since they are Verilog95, most simulators support it and the
reading of the data for these commands can be done in a couple of lines
in the testbench without too much thought. The newer Verilog 2001 file
commands take a bit more thought and more typing to get to work but do
give added flexibility, especially if you want to read something other
than binary/hex, need to parse the file, need to write/update the file
or do anything more advanced than simply reading data and storing in an
array. Also, if you are reading in a lot of data, the new commands can
be more memory efficient since you can read in pieces at a time however
doing so can also slow down simulation since every time you go to the
disk to get or write information can stall the simulation from operating
at full speed (similar to going to swap/paging when you run low on
memory). In general though, anytime you read/write to a file, you can
slow down simulation so I generally try to use sparingly.

In terms of ModelSim support, it depends on which version of simulator
you are using. From the original post, it looks like Chris is using
5.7c which I am fairly sure supports most of the Verilog 2001 file I/O
commands. There is is a section in the new 6.2i Language Templates that
also explains the use of these new commands at: Verilog --> Simulation
Constructs --> System Tasks and Functions --> File I/O --> Read/Write to
a File. There should be enough information to get someone started with
this but may take a little trial and error to get fully working the way
you intend to use it (at least that is how it usually works for me).

On a related but slightly off-topic note, Chris mentions that he is
using 5.2i but using 5.7c of ModelSim-XE. If memory serves, 5.7c was
the version of ModelSim-XE designed to be used with 6.1i. It is
important to keep the MTI-XE release in sync with the ISE version used
because MTI-XE comes with pre-compiled libraries for the version of ISE
it is released with. It is possible problems can arise later when
post-translate, post-map or post-par (timing) simulation is performed as
the simulation netlist will be created by 5.2i but the pre-compiled
libraries are for 6.1i if MTI-XE 5.7c is used. Since updates are
periodically necessary in the timing parameters and interfaces to the
models, it is never suggested to mix netlists generated with one version
of ISE with libraries from another.

Good luck,

-- Brian
 
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