Trouble with files

S

sr

Guest
When I try to compile the below package , it gives me the error
"Actual for formal f is not a file" whenever readline or writeline is called
when compiling in Modelsim.
Am I doing something wrong here? Can someone please help me out.

Thanks,
SR

library IEEE;
use IEEE.std_logic_1164.all;
use STD.textio.all;

package classio is
procedure read_v1d (variable f: in text; v : out std_logic_vector);
procedure write_v1d (variable f:eek:ut text; v : in std_logic_vector);
end package classio;
---------------
package body classio is
procedure read_v1d (variable f:in text; v : out std_logic_vector) is
variable buf: line;
variable c : character;

begin
readline(f, buf);-- This line causes the error
for i in v'range loop
read(buf, c);
case c is
when 'X' => v (i) := 'X';
when 'U' => v (i) := 'U';
when 'Z' => v (i) := 'Z';
when '0' => v (i) := '0';
when '1' => v (i) := '1';
when '-' => v (i) := '-';
when 'W' => v (i) := 'W';
when 'L' => v (i) := 'L';
when 'H' => v (i) := 'H';
when others => v (i) := '0';
end case;
end loop;
end procedure read_v1d;

procedure write_v1d (variable f: out text; v : in std_logic_vector) is
variable buf: line;
variable c : character;

begin
for i in v'range loop
case v(i) is
when 'X' => write(buf, 'X');
when 'U' => write(buf, 'U');
when 'Z' => write(buf, 'Z');
when '0' => write(buf, character'('0'));
when '1' => write(buf, character'('1'));
when '-' => write(buf, '-');
when 'W' => write(buf, 'W');
when 'L' => write(buf, 'L');
when 'H' => write(buf, 'H');
when others => write(buf, character'('0'));
end case;
end loop;
writeline (f, buf); --This line causes the error!
end procedure write_v1d;
end package body classio;
 
"sr" <gtg418c@mail.gatech.edu> wrote in message
news:bf72li$g9u$1@news-int.gatech.edu...
When I try to compile the below package , it gives me the error
"Actual for formal f is not a file" whenever readline or writeline
is called
when compiling in Modelsim.
Am I doing something wrong here? Can someone please help me out.

Thanks,
SR
Click to expand...
Are you using VHDL 93 or VHDL 87? In VHDL 93, a new type of object,
the file, was added. A file must be passed to a procedure
formal parameter of class file, e.g.

procedure read_v1d (file f:in text; v : out std_logic_vector) is
^^^^

In VHDL 87 there was no file class, so files were associated with
variables as you've attempted to do,

regards

Alan

<snip>

--
Alan Fitch
Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project
Services

Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24
1AW, UK
Tel: +44 (0)1425 471223 mail:
alan.fitch@doulos.com
Fax: +44 (0)1425 471573 Web:
http://www.doulos.com

The contents of this message may contain personal views which are not
the
views of Doulos Ltd., unless specifically stated.
 
Anyone?

Thanks,
SR
"sr" <gtg418c@mail.gatech.edu> wrote in message
news:bf92ev$fe9$1@news-int.gatech.edu...
I am using VHDL 93 . But when I try to declare it as file class, it gives
me
the errors "file interface declaration must not contain a mode" and
"parameter kinds do not conform for f".

Really appreciate the help.

Thanks,
SR

"Alan Fitch" <alan.fitch@doulos.com> wrote in message
news:bf8bqu$dsg$1$830fa7b3@news.demon.co.uk...

"sr" <gtg418c@mail.gatech.edu> wrote in message
news:bf72li$g9u$1@news-int.gatech.edu...
When I try to compile the below package , it gives me the error
"Actual for formal f is not a file" whenever readline or writeline
is called
when compiling in Modelsim.
Am I doing something wrong here? Can someone please help me out.

Thanks,
SR


Are you using VHDL 93 or VHDL 87? In VHDL 93, a new type of object,
the file, was added. A file must be passed to a procedure
formal parameter of class file, e.g.

procedure read_v1d (file f:in text; v : out std_logic_vector) is
^^^^

In VHDL 87 there was no file class, so files were associated with
variables as you've attempted to do,

regards

Alan

snip

--
Alan Fitch
Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project
Services

Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24
1AW, UK
Tel: +44 (0)1425 471223 mail:
alan.fitch@doulos.com
Fax: +44 (0)1425 471573 Web:
http://www.doulos.com

The contents of this message may contain personal views which are not
the
views of Doulos Ltd., unless specifically stated.
Click to expand...
 
"sr" <gtg418c@mail.gatech.edu> wrote in message
news:bf92ev$fe9$1@news-int.gatech.edu...
I am using VHDL 93 . But when I try to declare it as file class, it
gives me
the errors "file interface declaration must not contain a mode" and
Click to expand...
Sorry, that was my mistake - you must not declare the parameter as
"in" or "out".
So the correct declarations are

procedure read_v1d (file f: text; v : out std_logic_vector);
procedure write_v1d (file f: text; v : in std_logic_vector);


"parameter kinds do not conform for f".
Click to expand...
"do not conform" means that the declaration and the definition
do not match. For instance, if you write

procedure read_v1d (file f: text;...

in the package and

procedure read_v1d (variable f: text; ...

then you will get the "does not conform error".

As I feel guilty for forgetting the mode problem, here's a corrected
version of your code (which compiles using vhdl 93).

regards

Alan

library IEEE;
use IEEE.std_logic_1164.all;
use STD.textio.all;

package classio is
procedure read_v1d (file f: text; v : out std_logic_vector);
procedure write_v1d (file f: text; v : in std_logic_vector);
end package classio;
---------------
package body classio is
procedure read_v1d (file f: text; v : out std_logic_vector) is
variable buf: line;
variable c : character;

begin
readline(f, buf);-- This line causes the error
for i in v'range loop
read(buf, c);
case c is
when 'X' => v (i) := 'X';
when 'U' => v (i) := 'U';
when 'Z' => v (i) := 'Z';
when '0' => v (i) := '0';
when '1' => v (i) := '1';
when '-' => v (i) := '-';
when 'W' => v (i) := 'W';
when 'L' => v (i) := 'L';
when 'H' => v (i) := 'H';
when others => v (i) := '0';
end case;
end loop;
end procedure read_v1d;

procedure write_v1d (file f: text; v : in std_logic_vector) is
variable buf: line;
variable c : character;

begin
for i in v'range loop
case v(i) is
when 'X' => write(buf, 'X');
when 'U' => write(buf, 'U');
when 'Z' => write(buf, 'Z');
when '0' => write(buf, character'('0'));
when '1' => write(buf, character'('1'));
when '-' => write(buf, '-');
when 'W' => write(buf, 'W');
when 'L' => write(buf, 'L');
when 'H' => write(buf, 'H');
when others => write(buf, character'('0'));
end case;
end loop;
writeline (f, buf); --This line causes the error!
end procedure write_v1d;
end package body classio;



Really appreciate the help.

Thanks,
SR
Click to expand...

--
Alan Fitch
Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project
Services

Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24
1AW, UK
Tel: +44 (0)1425 471223 mail:
alan.fitch@doulos.com
Fax: +44 (0)1425 471573 Web:
http://www.doulos.com

The contents of this message may contain personal views which are not
the
views of Doulos Ltd., unless specifically stated.
 
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