Trouble making signal assignments in a procedure

[Alex Rast]

I'm trying to write various procedures which map signals in various ways, but
for whatever reason, my synthesis tool (Synplify) is complaining.

For instance, if I have a procedure like this:

procedure MapVectorA2VectorB(signal InputVector : in std_logic_vector; signal
MappingVector : inout std_logic_vector) is

variable translated_index_num : integer;

begin
MapVector : for index_num in InputVector'RANGE loop
translated_index_num := {expression(index_num)}
MappingVector(translated_index_num) <= InputVector(index_num);
end loop;
end MapVectorA2VectorB;

Synplify complains that in the signal assignment statement, I should instead
have a :=. Where am I going awry?

I think, also, that you get the general idea of what I'm trying to achieve:
map or slice some signal onto some other signal in a non-obvious way. What
would be the best way to handle this situation with a generalised method, i.e.
one that wouldn't require you typing in the same code into multiple modules?

--
Alex Rast
ad.rast.7@nwnotlink.NOSPAM.com
(remove d., .7, not, and .NOSPAM to reply)

 

[Neo]

Cant make out any problems with code, umm.. it will be interesting to
know the reason.

 

[Mike Treseler]

Alex Rast wrote:

I'm trying to write various procedures which map signals in various ways, but
for whatever reason, my synthesis tool (Synplify) is complaining.

complaining in various ways, no doubt

For instance, if I have a procedure like this:

exactly like this?

procedure MapVectorA2VectorB(
signal InputVector : in std_logic_vector;
signal MappingVector : inout std_logic_vector) is
variable translated_index_num : integer;
begin
MapVector : for index_num in InputVector'RANGE loop

translated_index_num := {expression(index_num)}
That line needs some work ^ ^
MappingVector(translated_index_num) <= InputVector(index_num);
end loop;
end MapVectorA2VectorB;

Synplify complains that in the signal assignment statement, I should instead
have a :=. Where am I going awry?
Where you ran a synthesis without a simulation

or even a syntax check.

I think, also, that you get the general idea of what I'm trying to achieve:
map or slice some signal onto some other signal in a non-obvious way.

I must admit that it is non-obvious to me.

What
would be the best way to handle this situation with a generalised method, i.e.
one that wouldn't require you typing in the same code into multiple modules?

Consider posting a working design entity showing the
statements you wish to convert to procedures.

-- Mike Treseler

 

[Alex Rast]

at Thu, 18 Nov 2004 02:08:51 GMT in <yK2dnay3h8WrmQHcRVn-tg@comcast.com>,
mike_treseler@comcast.net (Mike Treseler) wrote :

Alex Rast wrote:
I'm trying to write various procedures which map signals in various
ways, but for whatever reason, my synthesis tool (Synplify) is
complaining.

complaining in various ways, no doubt

For instance, if I have a procedure like this:

exactly like this?

procedure MapVectorA2VectorB(
signal InputVector : in std_logic_vector;
signal MappingVector : inout std_logic_vector) is
variable translated_index_num : integer;
begin
MapVector : for index_num in InputVector'RANGE loop

translated_index_num :=
{expression(index_num)}
That line needs some work ^ ^
MappingVector(translated_index_num) <=
InputVector(index_num);
end loop;
end MapVectorA2VectorB;

I have it posted exactly as it is written, save only for the {expression
(index_num)} text, which I put in there because I'm using various
convoluted functions, and I wanted to spare people from getting bogged down
in trying to analyse the functions themselves. Since the error occurs no
matter what function I put, I can be pretty sure it's not the functions
themselves that are creating an issue. But I'm happy to show the same code,
complete with a specific function:

procedure MapVectorA2VectorB(signal InputVector : in std_logic_vector;
signal
MappingVector : inout std_logic_vector) is

variable translated_index_num : integer;

begin
MapVector : for index_num in InputVector'RANGE loop
translated_index_num := ((InputVector'LENGTH/2)*
(InputVector'LENGTH REM 2)) + (index_num/2);
MappingVector(translated_index_num) <= InputVector
(index_num);
end loop;
end MapVectorA2VectorB;

In this case the function remaps even-numbered signals to the lower half of
the range, odd-numbered signals to the upper half. But in any case exactly
what it does is immaterial, and let me stress that in any case I'd want to
be able to put any arbitrary function in that variable assignment. So
please don't spend a lot of time worrying about the variable assignment
function.

Synplify complains that in the signal assignment statement, I should
instead have a :=. Where am I going awry?
Where you ran a synthesis without a simulation
or even a syntax check.

Actually, I run Synplify because it's the fastest way to *get* a syntax
check (!). My design entry tool's syntax checker doesn't seem to unroll the
code, so that if you have a VHDL entity or component that relies on passing
parameters through generics to set up bus widths, logic structures, etc,
that syntax checker invariably tells you there's an error even when the
code is good (i.e. when it synthesizes just fine and produces output that
works fine in hardware). So it's not reliable because there are too many
situations where I can't count on it to be giving an accurate syntax check.

Meanwhile, setting up a simulation takes far too much time, when you
consider than in only a few seconds or so I can run a synthesis and if it
dies on the syntax, I know right away (and it reports where it found the
error, too). So the Synplify syntax checker is the most reliable and
fastest way of checking for obvious problems.

--
Alex Rast
ad.rast.7@nwnotlink.NOSPAM.com
(remove d., .7, not, and .NOSPAM to reply)