Tristate Flip Flop

J

Jim

Guest
Hi

I want to implement a flip flop in my design, which can have a tristated
output. Here's how I'm thinking of doing it:

ff : process(CLK)
begin
if rising_edge(CLK) then
if OE = '0' then
Q <= 'Z';
else
Q <= D;
end if;
end if;
end process ff;


Is this the most efficient way of doing it? I'm using flip flops on the
inputs and outputs of my design so that I can meet the timing constraints.
Some of the outputs are shared by other devices and therefore need to be
tristated while not in use. I hoping someone can give me some feedback on
this.

Thanks in advance.
 
Jim wrote:
Hi

I want to implement a flip flop in my design, which can have a tristated
output. Here's how I'm thinking of doing it:

ff : process(CLK)
begin
if rising_edge(CLK) then
if OE = '0' then
Q <= 'Z';
else
Q <= D;
end if;
end if;
end process ff;


Is this the most efficient way of doing it? I'm using flip flops on the
inputs and outputs of my design so that I can meet the timing constraints.
Some of the outputs are shared by other devices and therefore need to be
tristated while not in use. I hoping someone can give me some feedback on
this.

Thanks in advance.
Click to expand...
Hi,

I can advice you to think RTL :
a flip-flop is a component, a tristate buffer is an other component.
-> so you have 2 components = 2 process

I will write :

-- your flip-flop
ff : process(CLK)
begin
if rising_edge(CLK) then
Q <= D; -- D_int is a new
end if;
end process ff;

-- your tristate
my_tristate_signal <= Q when OE = '1' ELSE 'Z';

JUST thinking RTL !

Laurent Gauch
www.amontec.com
_______________________________________________
VHDL MEMO
http://www.amontec.com/fix/vhdl_memo/index.html
 
Sylvain Munaut wrote:
Hi


I want to implement a flip flop in my design, which can have a tristated
output. Here's how I'm thinking of doing it:

ff : process(CLK)
begin
if rising_edge(CLK) then
if OE = '0' then
Q <= 'Z';
else
Q <= D;
end if;
end if;
end process ff;


Is this the most efficient way of doing it? I'm using flip flops on the
inputs and outputs of my design so that I can meet the timing
constraints.
Some of the outputs are shared by other devices and therefore need to be
tristated while not in use. I hoping someone can give me some
feedback on
this.


For these kind of stuff, the synthesis tools are pretty smart usually.

Some remarks :

* In most modern FPGA, tristate buffers are only available in IO blocks.
Internal tristate
are replaced by logic. So if it's for I/O that will be a real
tri-state. If it's internal,
it will be replaced by logic "simulating" the behaviour.

* The vhdl code you mentionned has a synchronous OE. I think most of the
tristate
buffers in IOB are asynchronous, so you will use two flip flops ( one
to register the OE).
You can have it asynchronous with

ff: process(clk,oe)
begin
if oe = '0' then
q <= 'Z';
elsif rising_edge(clk) then
q <= d;
end if;
end process;

It depends on the behaviour you want ...


Sylvain Munaut
Click to expand...
I am not OK with your "In most modern FPGA, tristate buffers are only
available in IO blocks".

In most modern FPGAs, we have internal tristate buffer. Not true for old
FPGAs.
The use of internal tristate buffers can be just nice to gain on slice
number for data mux.
So, all GOOD synthesizers schould be able to convert tristate to mux,
like XST or Leonardo Spectrum.

Laurent
www.amontec.com
 
* The vhdl code you mentionned has a synchronous OE. I think most of the
tristate
buffers in IOB are asynchronous, so you will use two flip flops ( one
to register the OE).
Click to expand...
Hold that ... At least in spartan 3 IOBs, there apparently is dedicated
flip/flops for the OE. And it can be synchronous or asynchronous OE.
 
Laurent Gauch wrote:
Hi,

I can advice you to think RTL :
a flip-flop is a component, a tristate buffer is an other component.
-> so you have 2 components = 2 process

I will write :

-- your flip-flop
ff : process(CLK)
begin
if rising_edge(CLK) then
Q <= D; -- D_int is a new
end if;
end process ff;

-- your tristate
my_tristate_signal <= Q when OE = '1' ELSE 'Z';

JUST thinking RTL !
Click to expand...
Hi,

Sorry, but I don't get.

Can you explain why this is not RTL?

ff : process(CLK)
begin
if rising_edge(CLK) then
if OE = '0' then
Q <= 'Z';
else
Q <= D;
end if;
end if;
end process ff;
Click to expand...

Fran.
 
These are alternate descriptions of the same thing.
The first is at a schematic level.
The second is a single process.
Either will work fine.

-- Mike Treseler
 
"Jim" <jim@notemail.com> writes:
I want to implement a flip flop in my design, which can have a tristated
output. Here's how I'm thinking of doing it:

ff : process(CLK)
begin
if rising_edge(CLK) then
if OE = '0' then
Q <= 'Z';
else
Q <= D;
end if;
end if;
end process ff;

Is this the most efficient way of doing it?
Click to expand...
Do you really want the OE to be registered as well, so that changes to
OE only take effect on a rising edge of the clock? Usually I want
OE to be asynchronous. It's easiest to implement this as a separate
FF and three-state buffer:

ff : process(CLK)
begin
if rising_edge(CLK) then
Q0 <= D;
end if;
end process ff;

Q1 <= 'Z' when OE = '0' else Q0;
 
Registering OE doesn't cost any time in this case
since the data is registered. It might eliminate
some bus contention and glitches.

-- Mike Treseler
 
I prefer the first solution, cause it is better to register each output for
timing constraint. For solution 2, there are some combi. logic before
output.

"mike_treseler" <tres@fl_ke.com> wrote in message
news:9648a887892454255b42e3dd9cedb9e5@localhost.talkaboutprogramming.com...
These are alternate descriptions of the same thing.
The first is at a schematic level.
The second is a single process.
Either will work fine.

-- Mike Treseler
Click to expand...
 
Hi


I want to implement a flip flop in my design, which can have a tristated
output. Here's how I'm thinking of doing it:

ff : process(CLK)
begin
if rising_edge(CLK) then
if OE = '0' then
Q <= 'Z';
else
Q <= D;
end if;
end if;
end process ff;


Is this the most efficient way of doing it? I'm using flip flops on the
inputs and outputs of my design so that I can meet the timing constraints.
Some of the outputs are shared by other devices and therefore need to be
tristated while not in use. I hoping someone can give me some feedback on
this.
Click to expand...
For these kind of stuff, the synthesis tools are pretty smart usually.

Some remarks :

* In most modern FPGA, tristate buffers are only available in IO blocks. Internal tristate
are replaced by logic. So if it's for I/O that will be a real tri-state. If it's internal,
it will be replaced by logic "simulating" the behaviour.

* The vhdl code you mentionned has a synchronous OE. I think most of the tristate
buffers in IOB are asynchronous, so you will use two flip flops ( one to register the OE).

You can have it asynchronous with

ff: process(clk,oe)
begin
if oe = '0' then
q <= 'Z';
elsif rising_edge(clk) then
q <= d;
end if;
end process;

It depends on the behaviour you want ...


Sylvain Munaut
 
"Amontec, Larry" wrote:
Sylvain Munaut wrote:
Hi


I want to implement a flip flop in my design, which can have a tristated
output. Here's how I'm thinking of doing it:

ff : process(CLK)
begin
if rising_edge(CLK) then
if OE = '0' then
Q <= 'Z';
else
Q <= D;
end if;
end if;
end process ff;


Is this the most efficient way of doing it? I'm using flip flops on the
inputs and outputs of my design so that I can meet the timing
constraints.
Some of the outputs are shared by other devices and therefore need to be
tristated while not in use. I hoping someone can give me some
feedback on
this.


For these kind of stuff, the synthesis tools are pretty smart usually.

Some remarks :

* In most modern FPGA, tristate buffers are only available in IO blocks.
Internal tristate
are replaced by logic. So if it's for I/O that will be a real
tri-state. If it's internal,
it will be replaced by logic "simulating" the behaviour.

* The vhdl code you mentionned has a synchronous OE. I think most of the
tristate
buffers in IOB are asynchronous, so you will use two flip flops ( one
to register the OE).
You can have it asynchronous with

ff: process(clk,oe)
begin
if oe = '0' then
q <= 'Z';
elsif rising_edge(clk) then
q <= d;
end if;
end process;

It depends on the behaviour you want ...


Sylvain Munaut

I am not OK with your "In most modern FPGA, tristate buffers are only
available in IO blocks".

In most modern FPGAs, we have internal tristate buffer. Not true for old
FPGAs.
The use of internal tristate buffers can be just nice to gain on slice
number for data mux.
So, all GOOD synthesizers schould be able to convert tristate to mux,
like XST or Leonardo Spectrum.

Laurent
www.amontec.com
Click to expand...
You might want to check your more recent Xilinx parts, the Spartan 3 and
Virtex 4. Neither has internal tri-state buffers. Xilinx has been
reducing the number of tbufs from 1 per LUT/FF in the XC4000 series to 1
per four LUT/FF in the XC2V parts. In all new Xilinx parts they are
absent. Altera has not had them in a long time if ever.

--

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX
 
"F.Camarero" wrote:
Laurent Gauch wrote:

Hi,

I can advice you to think RTL :
a flip-flop is a component, a tristate buffer is an other component.
-> so you have 2 components = 2 process

I will write :

-- your flip-flop
ff : process(CLK)
begin
if rising_edge(CLK) then
Q <= D; -- D_int is a new
end if;
end process ff;

-- your tristate
my_tristate_signal <= Q when OE = '1' ELSE 'Z';

JUST thinking RTL !


Hi,

Sorry, but I don't get.

Can you explain why this is not RTL?
Click to expand...
He just means you are thinking in terms of what you want done, rather
than thinking in terms of the hardware you want built.

--

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX
 
mike_treseler wrote:
Registering OE doesn't cost any time in this case
since the data is registered. It might eliminate
some bus contention and glitches.
Click to expand...
But that depends on when the signals driving the tristate are availble.
If this is an external bus control I expect you don't want to delay it
by clocking.

--

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX
 
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