trireg

[Steve Hamm]

Hi
Please tell me what is the error in my code

module xyz(a,b,c)

inout a,b,c;

trireg a,b,c;

always
begin
a <= #2 0;
b <= #2 0;
c <= #2 0;
end

Can we assign a trireg variable in the above mentioned way.Verilog XL
is givin me an error saying that Illegal left hand side assignment.

Thanks in advance

Regards
Steve

 

[Shalom Bresticker]

A 'trireg' is of type net.

Procedural assignments in an always-begin-end block can be done only to
variables, not to nets.

Nets are assigned values using continuous assignments or as outputs of
primitives or port connections.

Shalom


Steve Hamm wrote:

Hi
Please tell me what is the error in my code

module xyz(a,b,c)

inout a,b,c;

trireg a,b,c;

always
begin
a <= #2 0;
b <= #2 0;
c <= #2 0;
end

Can we assign a trireg variable in the above mentioned way.Verilog XL
is givin me an error saying that Illegal left hand side assignment.

Thanks in advance

Regards
Steve

--
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Design & Reuse Methodology Tel: +972 9 9522268
Freescale Semiconductor Israel, Ltd. Fax: +972 9 9522890
POB 2208, Herzlia 46120, ISRAEL Cell: +972 50 5441478

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[Jonathan Bromley]

On 1 Sep 2004 11:54:27 -0700, hamm_steve@yahoo.com (Steve Hamm) wrote:

[...]

trireg a,b,c;

always
begin
a <= #2 0;
b <= #2 0;
c <= #2 0;
end

Can we assign a trireg variable in the above mentioned way.Verilog XL
is givin me an error saying that Illegal left hand side assignment.

It tells the truth.

trireg is a species of net, and nets cannot be assigned
in a procedural block (always or initial). You need
continuous assignment, or connection to a module output.

You also have a zero-delay loop in your always, but I guess
that's because you cut down your example for the posting.

inout ports are necessarily nets, and therefore it's never
possible to assign to them within a procedural block.
You probably need an auxiliary reg variable, assigned
in the always block, and then a continuous assign to
apply the value of that reg on to the inout port net.
--
Jonathan Bromley, Consultant

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[Metin Yerlikaya]

Hi,
as far as I know, trireg is net( a wire ) type in verilog.
But verilog needs a variable declared as register before you
can assign it in always block.
Hope this helps

Metin


hamm_steve@yahoo.com (Steve Hamm) wrote in message news:<a4ea06c0.0409011054.31d0c15e@posting.google.com>...

Hi
Please tell me what is the error in my code

module xyz(a,b,c)

inout a,b,c;

trireg a,b,c;

always
begin
a <= #2 0;
b <= #2 0;
c <= #2 0;
end

Can we assign a trireg variable in the above mentioned way.Verilog XL
is givin me an error saying that Illegal left hand side assignment.

Thanks in advance

Regards
Steve