trireg and nmos

[Pankaj Golani]

Hi all

I am facing some problem with the trireg variable and switch level
modeling in my code.The code is as follows

module xyz(A0,A1,B0,B1)

inout A0,A1,B0,B1;

trireg A0,A1,B0,B1;

nmos(A0 , GND,F0);
nmos(A1, GND, F0);
pmos(B0, VDD, D0);
pmos(B1, VDD, D1);

where F0,F1,D0,D1 are some internal nodes.But the problem is that
after initializing A0 = 1, A1 = 0 the correct result should be that
after some delay both A0 and A1 = 0 due to F0 =1 and B0 = 1 and B1 = 0
due to D0 = 1 and D1 = 0 but i am getting a X state in A0 and B0.

Am i doing something wrong.

Thanks
Regards
Pankaj Golani

 

[Steven Sharp]

pankajgolani_2000@yahoo.com (Pankaj Golani) wrote in message news:<f4bcea61.0408181048.5b6b4298@posting.google.com>...

trireg A0,A1,B0,B1;

nmos(A0 , GND,F0);
nmos(A1, GND, F0);
pmos(B0, VDD, D0);
pmos(B1, VDD, D1);

where F0,F1,D0,D1 are some internal nodes.But the problem is that
after initializing A0 = 1, A1 = 0 the correct result should be that
after some delay both A0 and A1 = 0 due to F0 =1 and B0 = 1 and B1 = 0
due to D0 = 1 and D1 = 0 but i am getting a X state in A0 and B0.

From what you have described, A0 should be 1. The fact that it is a
trireg should not matter when you are actively driving it. However, it
is possible that you have made a mistake elsewhere (possibly outside
this module) and are driving A0 with a 0 somewhere else, giving you
driver contention and an X value.

 

[Steven Sharp]

pankajgolani_2000@yahoo.com (Pankaj Golani) wrote in message news:<f4bcea61.0408181048.5b6b4298@posting.google.com>...

where F0,F1,D0,D1 are some internal nodes.But the problem is that
after initializing A0 = 1, A1 = 0 the correct result should be that
after some delay both A0 and A1 = 0 due to F0 =1

Oops, I said A0 should be 1, when I meant to agree with you that it
should be 0.

However, you said that you initialized A0 to 1. How did you do that,
and is it possible that your mechanism for initialization is still
driving a 1 onto A0? That would explain an X result.