Triggering OVL Library Assertions in Verilog.

Hi All,
I am new to assertion based verification. I am using NCVerilog compiler
(plus Simvision viewer) and Accellera OVL libraries.

Through a very primitive program, I am trying to trigger off the
assertions. First, the code. It's as below:

/******************************/
`define OVL_ASSERT_ON
`define OVL_INIT_MSG
`include "assert_always.vlib"

module temp;

integer b;

initial
b = 1'd0;

always @ (b)
$display ("%d", b);

initial //values made to change so that
begin //the assertions can trigger on them
#1 b = 'd2;
#1 b = 'd0;
#1 b = 'd7;
#1 b = 'd0;
#1 b = 'd9;
end

assert_always #( //OVL Library in-built assertion
`OVL_ERROR,
`OVL_ASSERT,
"Error: O/P is 0",
`OVL_COVER_ALL)

check ( //here, the first 2 fields say clk and reset_in.
, , b != 0 //there's no clk/reset in my prog, so I've left them blank.
); //the 3rd field is the expr that I want to trigger on.

endmodule
/******************************/

What I want to do is this:
1. I want to trigger the assertions whenever b equals 0.
2. I am purposely changing the value of b 5 times, and expecting the
assertion to trigger twice (for each of the 0 values).

The screen o/p I am getting is this:

OVL_NOTE: V1.6: ASSERT_ALWAYS initialized @ temp.check.ovl_init_msg_t
Severity: 1, Message: Error: O/P is 0
2
0
7
0
9
ncsim: *W,RNQUIE: Simulation is complete.

What I want to know is that, since b goes to 0 twice, why am I not
getting the assertion message twice.

I am sure that I am doing something wrong, either in the assert_always
# (... or in the check (... blocks. But I am not able to figure out
what exactly it is.

If someone could explain this to me, I would be really, REALLY
grateful.

Thanks in advance,
Amit.

 

[Alex]

check ( //here, the first 2 fields say clk and reset_in.
, , b != 0 //there's no clk/reset in my prog, so I've left them blank.
); //the 3rd field is the expr that I want to trigger on.

Assertions can work without local reset (using global reset) but they
cannot work without the clock.
You must create clock and supply it to assertion.

Regards,
-Alex

 

Alex wrote:

check ( //here, the first 2 fields say clk and reset_in.
, , b != 0 //there's no clk/reset in my prog, so I've left them blank.
); //the 3rd field is the expr that I want to trigger on.

Assertions can work without local reset (using global reset) but they
cannot work without the clock.
You must create clock and supply it to assertion.

Regards,
-Alex

Hi Alex,
Thank you very much !

I wrote another example altogether using both a clock as well as a
reset and supplied them to the check ( ) instance and the assertions
triggered off at the correct places at the right times.

Thanks once again.

Best regards,
Amit.