translating .jed files to equations

[john williams]

I am writing a VHDL model of an old cypress PLD (CY7C331). Does
anybody know of any programs which which generate equations from .jed
files for this device?

I have completed the translation by hand but am getting unexpected
results and I cannot get any help from Cypress because they say the
part is too old. If there are no programs which will do this a
programmer's or user's manual for that chip would be extremely
helpful.

thanks

john

 

[jim granville]

john williams wrote:

I am writing a VHDL model of an old cypress PLD (CY7C331). Does
anybody know of any programs which which generate equations from .jed
files for this device?

I have completed the translation by hand but am getting unexpected
results and I cannot get any help from Cypress because they say the
part is too old. If there are no programs which will do this a
programmer's or user's manual for that chip would be extremely
helpful.

These older PLDs tend to be highly regular.
Do you still have tool flow for the device ? - that can help
confirm unsure FUSE mappings, by using some simple code-deltas.

Also, either with that older tool flow (or even manually on a device
programmer) you can generate device test patterns, which can also help
confirm (with a working device) that 'what you think the logic is',
does indeed pass the vector tests.

-jg

 

[Amontec Team, Laurent Gau]

jim granville wrote:

john williams wrote:

I am writing a VHDL model of an old cypress PLD (CY7C331). Does
anybody know of any programs which which generate equations from .jed
files for this device?

I have completed the translation by hand but am getting unexpected
results and I cannot get any help from Cypress because they say the
part is too old. If there are no programs which will do this a
programmer's or user's manual for that chip would be extremely
helpful.


These older PLDs tend to be highly regular.
Do you still have tool flow for the device ? - that can help
confirm unsure FUSE mappings, by using some simple code-deltas.

Also, either with that older tool flow (or even manually on a device
programmer) you can generate device test patterns, which can also help
confirm (with a working device) that 'what you think the logic is',
does indeed pass the vector tests.

-jg

If you know the specification of your old design, this will be better to

re-write the VHDL source ... you will save many flops in the PLD.

Test patterns for reversing your .jed will be too dangerous.

Laurent
www.amontec.com