translate verilog2001 to verilog1995

[bullfrog]

Hi:
I want to synthesis my design written in verilog-2001 on Synopsys
PRESTO.
But it seems to don't understand my syntax (ex. constant function). I
have verified my RTL on the Modelsim. Is there any tool can help me
translate my v2001 code to v1995 (in other words: unroll my verilog
code). All my design is clean if the parameters are defined.

I have found verilog prepocessor such as vppp. But I prefer verilog
2001 syntax. I want some tools to help me to synthesis my v2001 code.

Is there any idea?

Thanks.

--
Jay
National Sun-Yat-Sen University , Taiwan

 

[eda_employee]

I want to synthesis my design written in verilog-2001 on Synopsys
PRESTO.
But it seems to don't understand my syntax (ex. constant function). I
have verified my RTL on the Modelsim. Is there any tool can help me
translate my v2001 code to v1995 (in other words: unroll my verilog
code). All my design is clean if the parameters are defined.

I have found verilog prepocessor such as vppp. But I prefer verilog
2001 syntax. I want some tools to help me to synthesis my v2001 code.

In general, no. If you are using constant-functions (function integer ..)
to initialize synthesized parameter-values, then you'll probably have
to re-write the RTL to avoid the constant-functions.

Few synthesis tools accept constant functions. As a matter of fact,
even in VHDL, which has supported functions for a very long time,
constants initialized by function-calls still cause problems in
modern synthesis tools.

I assume you've tried to replace the constant-functions with
Verilog-macros?
This might work for *simple* arithmetic operations.


// Example
`define MAX2( x, y ) ( ((x)>) ? (x) : ) // return maximum of (x,y)

....

parameter BUSA_W = 16;
parameter BUSB_W = 32;

parameter DATA_W = `MAX2( BUSA_W, BUSB_W ); // '32'

 

thx for your reply

but my constant function is not so easy as the constant function , for
example log2, it need some variabe to save the temp variables and a
loop.

This is more complex in my design I need to decide parameters in the
generate for loop to create the instance such like this:


genvar i;
generate
for(i=1; i<=LEVEL; i=i+1)
begin: row_cell
lzc_row #(.IN_WIDTH(level_out_width(IN_WIDTH,i)), .LEVEL(i))
row (,);
end
endgenerate

LEVEL is a localparam and IN_WIDTH is a parameter

 

Some functions like log2 are actually practical to implement with
macros using a sequence of conditional operators. For a 32-bit integer
input, there are only 32 possible output values, and you only need 32
conditional operators to decide which one. Such a brute-force solution
might require a 16-line macro, but you only have to write it once.

This also works for any other situation that requires selecting among a
relatively small number of output values based on what range the input
value falls into. It isn't elegant, but it works.