Transition Coverage in SV

[Shenli]

Hi all,

Can I use cover in SV assertion to imitate transition coverage of
functional coverage.

For example,
covergroup port_cg;
coverpoint port_cp {
bins t1 = (0=>1), (2=>1);
}
endgroup

Any suggestions are welcome!
Best regards,
Davy

 

[Jonathan Bromley]

On Tue, 26 Jun 2007 01:56:20 -0700,
Shenli <zhushenli@gmail.com> wrote:

Hi all,

Just a thought: Do you follow the Verification Guild? Many
of your recent questions have related to verification
methodology. There are some great methodology discussions
on that forum http://verificationguild.com/

Can I use cover in SV assertion to imitate transition coverage of
functional coverage.

Yes - I think I suggested this in an earlier post.
There is a very close relationship between coverpoint transitions
and sequence coverage. Choose whichever form is most convenient
for your specific application. Typically, SVA sequences are
better when you want to describe complicated temporal behaviour
or your sequence involves many different signals; coverpoints
are better when you need to cover many different sequences,
each of which is fairly simple. In most tools there is a
common coverage database - so the final coverage analysis is
the same in both cases.

For example,
covergroup port_cg;
coverpoint port_cp {
bins t1 = (0=>1), (2=>1);
}
endgroup

sequence t1_0_1;
(port_cp == 0) ##1 (port_cp == 1);
endsequence

sequence t1_2_1;
(port_cp == 2) ##1 (port_cp == 1);
endsequence

port_cg_bins_port_cp_t1: cover property (t1_0_1 or t1_2_1);

You'll need a clock.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.