Transfer data from one clock domain to another clock created

[Benjamin Couillard]

Hi everyone, I've got a question.

Let's say I have a PLL that generates a 100 MHz clock and a 200 MHz
clock. The clocks are in phase, i.e. a rising edge on the 100 MHz
occurs at the same time as a rising edge 200 MHz clock.

.. In my application I want to process the data @ 200 MHz to reduce
filter complexity, i.e. my filters would use only half of the
multipliers compared to running the filters @ 100 MHz. However, the
effective sampling rate would remain the same i.e. 100 MHz. I need to
obtain a data valid signal enabled 50% of the time, since there would
be a new data 1 cycle out of 2 on the 200 MHz clock.

I could use an asynchronous FIFO to get the data valid @ 200 MHz, but
I think this solution is overkill since both clocks are in phase-lock.

What would you do? I want the data valid to be enabled 50% of the
time, and I want the data_valid to be '1' when my 16 bits data sample
change.


Best regards

Benjamin

 

[Nico Coesel]

Benjamin Couillard <benjamin.couillard@gmail.com> wrote:

Hi everyone, I've got a question.

Let's say I have a PLL that generates a 100 MHz clock and a 200 MHz
clock. The clocks are in phase, i.e. a rising edge on the 100 MHz
occurs at the same time as a rising edge 200 MHz clock.

. In my application I want to process the data @ 200 MHz to reduce
filter complexity, i.e. my filters would use only half of the
multipliers compared to running the filters @ 100 MHz. However, the
effective sampling rate would remain the same i.e. 100 MHz. I need to
obtain a data valid signal enabled 50% of the time, since there would
be a new data 1 cycle out of 2 on the 200 MHz clock.

I could use an asynchronous FIFO to get the data valid @ 200 MHz, but
I think this solution is overkill since both clocks are in phase-lock.

What would you do? I want the data valid to be enabled 50% of the
time, and I want the data_valid to be '1' when my 16 bits data sample
change.

I'd use a timing constrain. If the tools know about the clocks coming
from inside the FPGA the tools might create the timing constraints
automatically based on the input clock. I know the XIlinx tools create
such contraints automatically.

--
Failure does not prove something is impossible, failure simply
indicates you are not using the right tools...
nico@nctdevpuntnl (punt=.)
--------------------------------------------------------------

 

[Rob Gaddi]

On 1/4/2011 12:34 PM, Benjamin Couillard wrote:

Hi everyone, I've got a question.

Let's say I have a PLL that generates a 100 MHz clock and a 200 MHz
clock. The clocks are in phase, i.e. a rising edge on the 100 MHz
occurs at the same time as a rising edge 200 MHz clock.

. In my application I want to process the data @ 200 MHz to reduce
filter complexity, i.e. my filters would use only half of the
multipliers compared to running the filters @ 100 MHz. However, the
effective sampling rate would remain the same i.e. 100 MHz. I need to
obtain a data valid signal enabled 50% of the time, since there would
be a new data 1 cycle out of 2 on the 200 MHz clock.

I could use an asynchronous FIFO to get the data valid @ 200 MHz, but
I think this solution is overkill since both clocks are in phase-lock.

What would you do? I want the data valid to be enabled 50% of the
time, and I want the data_valid to be '1' when my 16 bits data sample
change.


Best regards

Benjamin

Put a T flop on the 100 MHz clock. Now you've got a 50 MHz square wave,
changing state every time you get a 100 MHz rising edge. Reregister
that to the rising edge of the 200 MHz clock, now you've got a 50 MHz
square wave changing state on every falling edge of the 100 MHz clock.
XOR that with the previous value and reregister on the rising edge of
the 200 MHz clock, now you've got a 100 MHz signal that the tools
recognize as being on the 200 MHz clock domain that tells you which
phase of the 100 MHz clock you're in. Distribute as needed.

Or something like that.

--
Rob Gaddi, Highland Technology
Email address is currently out of order

 

[Benjamin Couillard]

On Jan 4, 3:42 pm, n...@puntnl.niks (Nico Coesel) wrote:

Benjamin Couillard <benjamin.couill...@gmail.com> wrote:
Hi everyone, I've got a question.

Let's say I have a PLL that generates a 100 MHz clock and a 200 MHz
clock. The clocks are in phase, i.e. a rising edge on the 100 MHz
occurs at the same time as a rising edge 200 MHz clock.

. In my application I  want to process the data @ 200 MHz to reduce
filter complexity, i.e. my filters would use only half of the
multipliers compared to running the filters @ 100 MHz. However, the
effective sampling rate would remain the same i.e. 100 MHz.  I need to
obtain a data valid signal enabled 50% of the time, since there would
be a new data 1 cycle out of 2 on the 200 MHz clock.

I could use an asynchronous FIFO to get the data valid @ 200 MHz, but
I think this solution is overkill since both clocks are in phase-lock.

What would you do? I want the data valid to be enabled 50% of the
time, and I want the data_valid to be '1' when my 16 bits data sample
change.

I'd use a timing constrain. If the tools know about the clocks coming
from inside the FPGA the tools might create the timing constraints
automatically based on the input clock. I know the XIlinx tools create
such contraints automatically.

--
Failure does not prove something is impossible, failure simply
indicates you are not using the right tools...
nico@nctdevpuntnl (punt=.)
--------------------------------------------------------------

The first thing I tried is this



DATA_VAL_200M <= DATA_VAL_100M and CLK_100M.

Then I use this signal as a data_valid signal for my filter core
running @ 200 MHz but with a sample rate of 100 MHz.


It seems to work fine in synthesis i.e. Xilinx doesn't complain and
does not output a warming, however in simulation I get some
"glitches", basically I sometimes see a small red line at transitions.
I think this is related to "delta cycles" in VHDL but I could be
mistaken.

Does anyone have a (better) solution?

 

[Andy]

OK, data is valid on the rising edge of 100M, right?

Is it still valid (same data) on the falling edge too?

If so, it really does not matter which edge of 100M you sample the data into your 200M domain does it? You just need to make sure you don't sample the same 100M data twice in 200M domain.

Just set up a 200M signal that toggles every 200M clock. Use that as data valid. It does not matter which edge of 100M it is aligned with.

Andy

p.s. OK, it might matter if you are having problems making timing from the falling edge of 100m to the rising edge of 200M, but that is unlikely if the rest of it is all running at 200 anyway.

 

[Mike Treseler]

On 1/4/2011 12:50 PM, Benjamin Couillard wrote:

The first thing I tried is this
DATA_VAL_200M<= DATA_VAL_100M and CLK_100M.

The suggestion above was a constraint, not a gated clock.

Then I use this signal as a data_valid signal for my filter core
running @ 200 MHz but with a sample rate of 100 MHz.
Does anyone have a (better) solution?

I would use a synchronous design with only one clock, 200Mhz.
No constraints necessary.

-- Mike Treseler

 

[Benjamin Couillard]

On 4 jan, 19:04, Mike Treseler <mtrese...@gmail.com> wrote:

On 1/4/2011 12:50 PM, Benjamin Couillard wrote:

The first thing I tried is this
DATA_VAL_200M<= DATA_VAL_100M and CLK_100M.

The suggestion above was a constraint, not a gated clock.

I'm aware, though, I only added this "solution" to explain what I had
done so far. I will try the previous solutions

Then I use this signal as a data_valid signal for my filter core
running @ 200 MHz but with a sample rate of 100 MHz.
Does anyone have a (better) solution?

I would use a synchronous design with only one clock, 200Mhz.
No constraints necessary.

            -- Mike Treseler

In a perfect world, that's what I would do, but this is not a new
design, I need to add processing blocks in an almost finished FPGA.
Almost everything else in on the 100 MHz clock. In order to save some
space on the FPGA,my plan was to transfer the data to the 200 MHz
clock, perform the filtering operations, and then align the data to
the 100 MHz clock (by converting the data_out_valid on 200 MHz to 100
MHz). That way I will use less resources than performing the filtering
operations at 100 MHz.

 

[jc]

On Jan 4, 9:06 pm, Benjamin Couillard <benjamin.couill...@gmail.com>
wrote:

On 4 jan, 19:04, Mike Treseler <mtrese...@gmail.com> wrote:

On 1/4/2011 12:50 PM, Benjamin Couillard wrote:

The first thing I tried is this
DATA_VAL_200M<= DATA_VAL_100M and CLK_100M.

The suggestion above was a constraint, not a gated clock.

I'm aware, though, I only added this "solution" to explain what I had
done so far. I will try the previous solutions



Then I use this signal as a data_valid signal for my filter core
running @ 200 MHz but with a sample rate of 100 MHz.
Does anyone have a (better) solution?

I would use a synchronous design with only one clock, 200Mhz.
No constraints necessary.

            -- Mike Treseler

In a perfect world, that's what I would do, but this is not a new
design, I need to add processing blocks in an almost finished FPGA.
Almost everything else in on the 100 MHz clock. In order to save some
space on the FPGA,my plan was to transfer the data to the 200 MHz
clock, perform the filtering operations, and then align the data to
the 100 MHz clock (by converting the data_out_valid on 200 MHz to 100
MHz). That way I will use less resources than performing the filtering
operations at 100 MHz.

I think Andy nailed it. A simple, continuous toggle flop in the 200
MHz domain could serve as your data valid in that domain. You can run
your 100 MHz-generated data right on through assuming that par tools
will time 100MHz and 200 MHz domains together (which should occur
automatically if you set up your constraint to the input of the dcm,
which should propagate to its outputs). If for any reason the data
doesn't last for the entire 100 Mhz cycle, simply re-register when it
is valid at 100 MHz and use THAT data instead.

If for whatever reason your data source has gaps (i.e. stalls), maybe
you'd want to use a dual-port (dual-clocked) buffer in between domains
anyway and allow the read port (200 MHz domain) extract the data as it
becomes available.

- John

 

[Mike Treseler]

I would use a synchronous design with only one clock, 200Mhz.
No constraints necessary.

-- Mike Treseler

On 1/4/2011 6:06 PM, Benjamin Couillard wrote:

In a perfect world, that's what I would do, but this is not a new
design, I need to add processing blocks in an almost finished FPGA.
Almost everything else in on the 100 MHz clock. In order to save some
space on the FPGA,my plan was to transfer the data to the 200 MHz
clock, perform the filtering operations, and then align the data to
the 100 MHz clock (by converting the data_out_valid on 200 MHz to 100
MHz). That way I will use less resources than performing the filtering
operations at 100 MHz.

Either strategy can be made to work. The question is which will take
longer to design and debug.

Adding a fifo where there was none before, adds several reset test cases
to consider. These cases are often found late in the game. That's why I
might spend some time to create synchronous clock enables for the "known
good" 100MHz rate stuff instead. That way I would also avoid having to
specify and test the PLL delay constraints.

Good luck.

-- Mike Treseler

 

[Nico Coesel]

Benjamin Couillard <benjamin.couillard@gmail.com> wrote:

On Jan 4, 3:42=A0pm, n...@puntnl.niks (Nico Coesel) wrote:
Benjamin Couillard <benjamin.couill...@gmail.com> wrote:
Hi everyone, I've got a question.

Let's say I have a PLL that generates a 100 MHz clock and a 200 MHz
clock. The clocks are in phase, i.e. a rising edge on the 100 MHz
occurs at the same time as a rising edge 200 MHz clock.

. In my application I =A0want to process the data @ 200 MHz to reduce
filter complexity, i.e. my filters would use only half of the
multipliers compared to running the filters @ 100 MHz. However, the
effective sampling rate would remain the same i.e. 100 MHz. =A0I need to
obtain a data valid signal enabled 50% of the time, since there would
be a new data 1 cycle out of 2 on the 200 MHz clock.

I could use an asynchronous FIFO to get the data valid @ 200 MHz, but
I think this solution is overkill since both clocks are in phase-lock.

What would you do? I want the data valid to be enabled 50% of the
time, and I want the data_valid to be '1' when my 16 bits data sample
change.

I'd use a timing constrain. If the tools know about the clocks coming
from inside the FPGA the tools might create the timing constraints
automatically based on the input clock. I know the XIlinx tools create
such contraints automatically.
--------------------------------------------------------------

The first thing I tried is this



DATA_VAL_200M <=3D DATA_VAL_100M and CLK_100M.

Then I use this signal as a data_valid signal for my filter core
running @ 200 MHz but with a sample rate of 100 MHz.

It seems to work fine in synthesis i.e. Xilinx doesn't complain and
does not output a warming, however in simulation I get some
"glitches", basically I sometimes see a small red line at transitions.
I think this is related to "delta cycles" in VHDL but I could be
mistaken.

You probably get some glitches due to the AND operation. If the signal
meets setup and hold there is no problem. However I would implement an
edge detector in the 200MHz domain. Using the clock in an equation is
something Xilinx FPGAs don't like. There are few elements which allow
the clock to travel from a global clock net into a routing net. You
might end up using a lot of fast routing resources. AFAIK there is an
appnote on that subject.

--
Failure does not prove something is impossible, failure simply
indicates you are not using the right tools...
nico@nctdevpuntnl (punt=.)
--------------------------------------------------------------

 

[Mawa_fugo]

On Jan 4, 2:42 pm, n...@puntnl.niks (Nico Coesel) wrote:

Benjamin Couillard <benjamin.couill...@gmail.com> wrote:
Hi everyone, I've got a question.

Let's say I have a PLL that generates a 100 MHz clock and a 200 MHz
clock. The clocks are in phase, i.e. a rising edge on the 100 MHz
occurs at the same time as a rising edge 200 MHz clock.

. In my application I  want to process the data @ 200 MHz to reduce
filter complexity, i.e. my filters would use only half of the
multipliers compared to running the filters @ 100 MHz. However, the
effective sampling rate would remain the same i.e. 100 MHz.  I need to
obtain a data valid signal enabled 50% of the time, since there would
be a new data 1 cycle out of 2 on the 200 MHz clock.

I could use an asynchronous FIFO to get the data valid @ 200 MHz, but
I think this solution is overkill since both clocks are in phase-lock.

What would you do? I want the data valid to be enabled 50% of the
time, and I want the data_valid to be '1' when my 16 bits data sample
change.

I'd use a timing constrain. If the tools know about the clocks coming
from inside the FPGA the tools might create the timing constraints
automatically based on the input clock. I know the XIlinx tools create
such contraints automatically.

--
Failure does not prove something is impossible, failure simply
indicates you are not using the right tools...
nico@nctdevpuntnl (punt=.)
--------------------------------------------------------------

How do you feed the hungry monster ?

Do you mean you have 2 data channels comming @100 Mhz, then you plan
to use only one monster to eat the data at 200 Mhz ?

how many bytes per second, is depends on the monster