Top level in Verilog?

Hello,

I am new to Verilog, having just finished a book on the same.

I wanted to know the significance of top level ?

Intutively, it should mean the highest level of module, which links /
instantiates other lower modules. But I am not sure if that it the
meaning ?

Is it just a naming / programming convention that is followed while
writing in Verilog?



Any help would be appreciated.

Best Regards,
Jetli.

 

[Jonathan Bromley]

On Mon, 26 Nov 2007 17:30:34 -0800 (PST), rjetli@gmail.com wrote:

I wanted to know the significance of top level ?

Intutively, it should mean the highest level of module, which links /
instantiates other lower modules. But I am not sure if that it the
meaning ?

Yes, that's what people normally mean by "top level".

Is it just a naming / programming convention that is followed while
writing in Verilog?

It's a little more than that.

Traditional Verilog simulators (Verilog-XL, VCS) work
by reading *all* the Verilog source code in a simulation.
That source code contains a bunch of module definitions.
The simulator compiles all the modules, and then works out
how they're stitched together into a hierarchy. It does
that by starting from the top. But how do we decide which
is the top? Easy - it's the only module that is NOT
instantiated by any other module. Consider...

module Middle();
Bot1 b1(); // an instance of Bot1 within Middle
Bot2 b2(); // an instance of Bot2 within Middle
endmodule

module Bot1();
...
endmodule

module Bot2();
wire w; // I'll use this later
endmodule

module Top();
Middle m1();
Middle m2();
endmodule

The compiler sees 4 module definitions:
Middle, Bot1, Bot2, Top. It sees instances of Middle,
Bot1 and Bot2 within other modules. But there is NO
instance of Top !!! So the compiler assumes that Top
is the toplevel module, and builds the hierarchy:

Top
|_____m1
| |_b1
| |_b2
|
|_____m2
|_b1
|_b2

In fact, Verilog can build multiple parallel hierarchies
that work together. Suppose you added to the above code:

module Extra();
assign Top.m1.b2.w =1'b1;
endmodule

Just like Top, the new module Extra is not instantiated,
so it acts as a top level, sitting alongside Top.
The hierarchical name reference within Extra allows it
to communicate with the separate hierarchy that
is rooted in Top.

hth
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

 

[dash82]

On Nov 27, 2:51 am, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com>
wrote:

On Mon, 26 Nov 2007 17:30:34 -0800 (PST), rje...@gmail.com wrote:
I wanted to know the significance of top level ?

Intutively, it should mean the highest level of module, which links /
instantiates other lower modules. But I am not sure if that it the
meaning ?

Yes, that's what people normally mean by "top level".

Is it just a naming / programming convention that is followed while
writing in Verilog?

It's a little more than that.

Traditional Verilog simulators (Verilog-XL, VCS) work
by reading *all* the Verilog source code in a simulation.
That source code contains a bunch of module definitions.
The simulator compiles all the modules, and then works out
how they're stitched together into a hierarchy. It does
that by starting from the top. But how do we decide which
is the top? Easy - it's the only module that is NOT
instantiated by any other module. Consider...

module Middle();
Bot1 b1(); // an instance of Bot1 within Middle
Bot2 b2(); // an instance of Bot2 within Middle
endmodule

module Bot1();
...
endmodule

module Bot2();
wire w; // I'll use this later
endmodule

module Top();
Middle m1();
Middle m2();
endmodule

The compiler sees 4 module definitions:
Middle, Bot1, Bot2, Top. It sees instances of Middle,
Bot1 and Bot2 within other modules. But there is NO
instance of Top !!! So the compiler assumes that Top
is the toplevel module, and builds the hierarchy:

Top
|_____m1
| |_b1
| |_b2
|
|_____m2
|_b1
|_b2

In fact, Verilog can build multiple parallel hierarchies
that work together. Suppose you added to the above code:

module Extra();
assign Top.m1.b2.w =1'b1;
endmodule

Just like Top, the new module Extra is not instantiated,
so it acts as a top level, sitting alongside Top.
The hierarchical name reference within Extra allows it
to communicate with the separate hierarchy that
is rooted in Top.

hth
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.brom...@MYCOMPANY.comhttp://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

Thank you. That description was fabulous !