Tools & their SV Support

This is my Experience:

Mentor Precision 2007a.9:

surprisingly good, still not supporting some useful synthesis
constructs (i ran into nested interfaces being not supported)
Crashed with some synthesis constructs i have to avoid.

Synplify Pro 9.4:

surprisingly bad, lacking too much compared to the "old" Precision.
Seeedd to have problems with Macro's and the double backtick in them,
so i stopped my trial.

Modelsim SE:

Quite good as you should expect from a tool like this. But i didn't
put it much to the test (for synthesis constructs) as the synthesis
tools are the bottleneck.

Aldec Rivera:

I tested it and was disappointed by the SV support for verification.
Even my limited use of Classes (as a recent SV adopter) were'nt
accepted by the tool.

How are the experiences of others with tools claiming to support SV?

 

[Kevin Neilson]

info2@rayed.de wrote:

This is my Experience:

Mentor Precision 2007a.9:

surprisingly good, still not supporting some useful synthesis
constructs (i ran into nested interfaces being not supported)
Crashed with some synthesis constructs i have to avoid.

Synplify Pro 9.4:

surprisingly bad, lacking too much compared to the "old" Precision.
Seeedd to have problems with Macro's and the double backtick in them,
so i stopped my trial.

Modelsim SE:

Quite good as you should expect from a tool like this. But i didn't
put it much to the test (for synthesis constructs) as the synthesis
tools are the bottleneck.

Aldec Rivera:

I tested it and was disappointed by the SV support for verification.
Even my limited use of Classes (as a recent SV adopter) were'nt
accepted by the tool.

How are the experiences of others with tools claiming to support SV?

I've had a good experience with Synplify, using the features they say
are supported (enumerated types for FSMs, inferred connections in
instantiations, etc.) But the supported constructs are very few.

Judging from the amount of time it took to get 'generates' supported by
the synthesis tools, I'd say we have several years to go before we can
expect much support for SystemVerilog. -Kevin

 

[Jonathan Bromley]

On Thu, 24 Jul 2008 08:04:57 -0700 (PDT), info2@rayed.de wrote:

A well-known synthesis tool....

nested interfaces being not supported

When you say "nested interfaces", do you mean interface
instances in other interfaces? If so, I agree that's
a problem. But if you mean "nested interfaces" in
the sense of an interface that's DECLARED within the
code of another interface, then I don't know of any
simulators that support it either...

interface Outer;
logic Sig1; .....

interface Inner;
...
endinterface : Inner

...

endinterface : Outer

--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
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