Tool: Verilog testbench to time-voltage table

[arvan]

Is there any tool which can generate a TXT file that contains
time-voltage tables from Verilog testbench (signal generator file) ? I
want to use the TXT file as the signal generator in Spectre (Cadence)
for analog simulation (post-synthesis). So far I've always done
manually. But it will take long time if the number of the test is
longer.
TIA,
arvan

 

[arvan]

I've gotten another solution. I run my simulation with Modelsim and I
can use LIST menu to write the signals in tabular format. The strobe
delay is configurable, nice feature. case closed
arvan

 

[Ralf Hildebrandt]

arvan wrote:

Is there any tool which can generate a TXT file that contains
time-voltage tables from Verilog testbench (signal generator file) ? I
want to use the TXT file as the signal generator in Spectre (Cadence)
for analog simulation (post-synthesis).

I colleague in my company has written such a tool, but I guess, he will
not share it. So let me explain the idea behind (maybe this makes it
easier to write such a tool):

1) During simulation normal text-output is used: On every event of a
signal, that has to be monitored a text line is written, that contains
the actual time and the actual value of the signal.

2) A external converter tool (in the example: written in C) reads the
HDL text output and converts it in to the file format readable by the
file-controllable voltage source "vpwlf". The converter tool should be
started with the following parameters:
a) The voltage.
b) The time for a transition (low->high and high->low) = the slopes.
These parameters makes the tool target-independent.
For every bit a separate file for one vpwlf is needed. So the tool
should extract every bit from vectors and write it into a separate file.

Example (I don't have files at hand, so I have to remember it):
The text output from the HDL for one event looks like:
time signal-value

The file for the vpwlf for one event looks like:
time old voltage
time+transition new voltage


Notes:
1) The converter tool evaluates one text line and outputs two
vpwlf-commands: 1st the actual time and the actual voltage and 2nd the
actual time plus the transition time and the voltage after that
transition. But this may lead to problems, because during HDL simulation
multiple events may occur in a shorter time than the transition time
(hazards). I wrote an additional tool, that eliminates these hazards.
The drawback is, that not every transition can be handled.
The slopes are necessary, because otherwise power estimations are not
reliable.
2) Using an external tool for conversion has the advantage, that the
text output inside the HDL can be kept simple and independent from the
target library.


Ralf