R
Rhishi
Guest
Hi,
I've some structural verilog designs that use only verilog primitives
like "and", "or", "not" at the leaf level. And they use parameters and
generate statements of verilog 2001. What I want is to do a
"lightweight" synthesis i.e. just flatten the design and get one big
verilog module that contains only the basic gates. It need not (or
should not) do any optimizations, but should just flatten the design.
Is there a tool that can do this?
It would be like the post-synthesis simulation model generated by
Xilinx ISE. But problem with that is it's doing full fledged
synthesis, which I don't want and it has LUTs, not basic gates.
thanks,
Rhishikesh
I've some structural verilog designs that use only verilog primitives
like "and", "or", "not" at the leaf level. And they use parameters and
generate statements of verilog 2001. What I want is to do a
"lightweight" synthesis i.e. just flatten the design and get one big
verilog module that contains only the basic gates. It need not (or
should not) do any optimizations, but should just flatten the design.
Is there a tool that can do this?
It would be like the post-synthesis simulation model generated by
Xilinx ISE. But problem with that is it's doing full fledged
synthesis, which I don't want and it has LUTs, not basic gates.
thanks,
Rhishikesh