Tool to flatten a verilog design.

[Varun Jindal]

hello,
i am looking for a tool, which can flatten my verilog design,

i dont require the various heiarchies in the design and want to
flatten it into single top module design.


is anybody aware of such options in any available tool !?

thanks in advance,
regards
Varun.

 

[Narendran Kumaraguru Nath]

Hi,
I am really curious to find out why do you want to do such a thing?
The output of DC, after synthesis can be written out in such a form.
Thanks & Regards,
Naren.

varunjindal@yahoo.com (Varun Jindal) wrote in message news:<a132b4b3.0409140117.2e3a0824@posting.google.com>...

hello,
i am looking for a tool, which can flatten my verilog design,

i dont require the various heiarchies in the design and want to
flatten it into single top module design.


is anybody aware of such options in any available tool !?

thanks in advance,
regards
Varun.

 

[Petter Gustad]

varunjindal@yahoo.com (Varun Jindal) writes:

i am looking for a tool, which can flatten my verilog design,

I wrote such a tool around 1990, it was used to generate netlists for
the Dazix CAD system. Unfortunately, I don't have access the source
anymore. Writing such a program wasn't that difficult. Nowadays it's
probably simpler since you can find parsers available on the net. You
can also run your design through synthesis (works at least in Synopsys
Design Compiler) and flatten the design and write it out to a Verilog
file.

Petter

--
A: Because it messes up the order in which people normally read text.
Q: Why is top-posting such a bad thing?
A: Top-posting.
Q: What is the most annoying thing on usenet and in e-mail?

 

[Varun Jindal]

Well, if the problem statement requires the flattened netlist NOT to
be in form of logic gates ... i dont know if it can be done through
the Synopsys Design Compiler.

Say, in my top module i call two modules A and B. Both these modules
contain some information (say) info(A) and info(B).

now, i want the flattened netlist to be in this form

top module .. which contains info(A) and info(B) ... the port list of
top module in both the cases is similar.

i dnt wnat info(A) and info(B) to be decomposed into logic gates.



Regards,
Varun.



Petter Gustad <newsmailcomp6@gustad.com> wrote in message news:<87pt4kit7i.fsf@zener.home.gustad.com>...

varunjindal@yahoo.com (Varun Jindal) writes:

i am looking for a tool, which can flatten my verilog design,

I wrote such a tool around 1990, it was used to generate netlists for
the Dazix CAD system. Unfortunately, I don't have access the source
anymore. Writing such a program wasn't that difficult. Nowadays it's
probably simpler since you can find parsers available on the net. You
can also run your design through synthesis (works at least in Synopsys
Design Compiler) and flatten the design and write it out to a Verilog
file.

Petter

 

[Petter Gustad]

varunjindal@yahoo.com (Varun Jindal) writes:

Well, if the problem statement requires the flattened netlist NOT to
be in form of logic gates ... i dont know if it can be done through
the Synopsys Design Compiler.

You should be able to set the dont_touch attribute on the blocks that
you don't want to be compiled, even though I haven't tried just to
flatten a netlist without doing any compliation in DC myself.

Petter

--
A: Because it messes up the order in which people normally read text.
Q: Why is top-posting such a bad thing?
A: Top-posting.
Q: What is the most annoying thing on usenet and in e-mail?

 

[Swapnajit Mittra]

Petter Gustad <newsmailcomp6@gustad.com> wrote in message news:<877jqmp738.fsf@zener.home.gustad.com>...

varunjindal@yahoo.com (Varun Jindal) writes:

Well, if the problem statement requires the flattened netlist NOT to
be in form of logic gates ... i dont know if it can be done through
the Synopsys Design Compiler.

You should be able to set the dont_touch attribute on the blocks that
you don't want to be compiled, even though I haven't tried just to
flatten a netlist without doing any compliation in DC myself.

Petter

It seems to me that what Varun wants is a flattened *RTL* that
will retain all the RTL constructs (if, always, assign etc.) but
one that will have no hierarchies.

Varun, I can not think of a reason why you would need to do
this, but if this is indeed the case, then:

1. You need to build up the hierarchy tree.
2. Map the local name space within each module to a global
one. An obvious way to do this would be to map a local
variable name to its 'fullpath' (with adequate dose of '\').

I do not know of if such a tool exists, but this looks like an
interesting topic for an MS thesis.
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