Tool survey for syntax for formal => actual

[eadgbe]

I have a test case below that fails to compile in Modelsim. The issue revolves around
the use of expressions for actuals. Modelsim and I are at odds over the legality
of the syntax below. I've run the following code in Synplicity and Synopsys, and it
compiles and synthesizes successfully in both. If anyone out there has access to
any other tools to compile and/or synthesize this code, I'd appreciate the help. I need
ammo before I blast Mentor any further. Arguing the LRM is getting me nowhere.

I'll post my final results after I get this resolved.

Thanks, in advance,

Bob Luking


-- start of test case --

library ieee;
use ieee.std_logic_1164.all;

entity A is
port
(
A : in std_logic;
B : in std_logic;
C : in std_logic;
E : in std_logic_vector(15 downto 0);
F : in std_logic_vector(15 downto 0);

D : out std_logic
);
end A;

architecture rtl of A is
begin
D <= A xor B xor C xor E(0) xor F(0);
end rtl;

---------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;

entity Test is
port
(
X : in std_logic;
Y : in std_logic;
Q : in std_logic_vector(15 downto 0);

Z : out std_logic
);
end Test;

architecture RTL of Test is

component A is
port
(
A : in std_logic;
B : in std_logic;
C : in std_logic;
E : in std_logic_vector(15 downto 0);
F : in std_logic_vector(15 downto 0);

D : out std_logic
);
end component;

begin

U0 : A
port map
(
A => X and Y, -- relation and relation
B => not (X xor Y), -- not (relation and relation)
C => std_logic(Y), -- function_call(actual_designator)
E => x"430F", -- literal
F => '0' & Q(14 downto 0), -- aggregate

std_logic(D) => Z -- case of a function call on the formal part for an output port
);

end RTL;

-- end of test case --

 

[eadgbe]

Green Mountain VHDL Pro does not compile this code. Says the same thing Modelsim
does, that "actuals must be static".

Bob Luking

"eadgbe" <idont@thinkso.com> wrote in message news:Wbudnfj3dfsPe8KiU-KYuA@comcast.com...

I have a test case below that fails to compile in Modelsim. The issue revolves around
the use of expressions for actuals. Modelsim and I are at odds over the legality
of the syntax below. I've run the following code in Synplicity and Synopsys, and it
compiles and synthesizes successfully in both. If anyone out there has access to
any other tools to compile and/or synthesize this code, I'd appreciate the help. I need
ammo before I blast Mentor any further. Arguing the LRM is getting me nowhere.

I'll post my final results after I get this resolved.

Thanks, in advance,

Bob Luking


-- start of test case --

library ieee;
use ieee.std_logic_1164.all;

entity A is
port
(
A : in std_logic;
B : in std_logic;
C : in std_logic;
E : in std_logic_vector(15 downto 0);
F : in std_logic_vector(15 downto 0);

D : out std_logic
);
end A;

architecture rtl of A is
begin
D <= A xor B xor C xor E(0) xor F(0);
end rtl;

---------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;

entity Test is
port
(
X : in std_logic;
Y : in std_logic;
Q : in std_logic_vector(15 downto 0);

Z : out std_logic
);
end Test;

architecture RTL of Test is

component A is
port
(
A : in std_logic;
B : in std_logic;
C : in std_logic;
E : in std_logic_vector(15 downto 0);
F : in std_logic_vector(15 downto 0);

D : out std_logic
);
end component;

begin

U0 : A
port map
(
A => X and Y, -- relation and relation
B => not (X xor Y), -- not (relation and relation)
C => std_logic(Y), -- function_call(actual_designator)
E => x"430F", -- literal
F => '0' & Q(14 downto 0), -- aggregate

std_logic(D) => Z -- case of a function call on the formal part for an output
port
);

end RTL;

-- end of test case --

 

[MK]

for these 3 port maps you need additional signal + signal assignment
A => X and Y, --
relation and relation
B => not (X xor Y), -- not
(relation and relation)
F => '0' & Q(14 downto 0), --
aggregate

for example A => X_and_Y, (assignment: X_and_Y <= X and Y; )

this one should works - this is static expression
E => x"430F", --
literal

the two following should works - this is function conversion - first on
actual, second on formal
C => std_logic(Y), --
function_call(actual_designator)
std_logic(D) => Z -- case
of a function call on the formal part for an output port


Would be nice if VHDL has similar to Verilog behaviour in such cases
(such process is implicitly generated by simulator).

regards,
MK.


"eadgbe" <idont@thinkso.com> wrote in message
news:Wbudnfj3dfsPe8KiU-KYuA@comcast.com...

I have a test case below that fails to compile in Modelsim. The issue
revolves around
the use of expressions for actuals. Modelsim and I are at odds over the
legality
of the syntax below. I've run the following code in Synplicity and
Synopsys, and it
compiles and synthesizes successfully in both. If anyone out there has
access to
any other tools to compile and/or synthesize this code, I'd appreciate the
help. I need
ammo before I blast Mentor any further. Arguing the LRM is getting me
nowhere.

I'll post my final results after I get this resolved.

Thanks, in advance,

Bob Luking


-- start of test case --

library ieee;
use ieee.std_logic_1164.all;

entity A is
port
(
A : in std_logic;
B : in std_logic;
C : in std_logic;
E : in std_logic_vector(15 downto 0);
F : in std_logic_vector(15 downto 0);

D : out std_logic
);
end A;

architecture rtl of A is
begin
D <= A xor B xor C xor E(0) xor F(0);
end rtl;

---------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;

entity Test is
port
(
X : in std_logic;
Y : in std_logic;
Q : in std_logic_vector(15 downto 0);

Z : out std_logic
);
end Test;

architecture RTL of Test is

component A is
port
(
A : in std_logic;
B : in std_logic;
C : in std_logic;
E : in std_logic_vector(15 downto 0);
F : in std_logic_vector(15 downto 0);

D : out std_logic
);
end component;

begin

U0 : A
port map
(
A => X and Y, --
relation and relation
B => not (X xor Y), -- not
(relation and relation)
C => std_logic(Y), --
function_call(actual_designator)
E => x"430F", --
literal
F => '0' & Q(14 downto 0), --
aggregate

std_logic(D) => Z -- case
of a function call on the formal part for an output port
);

end RTL;

-- end of test case --

 

[eadgbe]

I understand your arguments. I humbly disagree. Synopsys and Synplicity both
disagree also. I'm trying to find out which tools take what position on this syntax.

Thanks for the reply.

Bob Luking


"MK" <nie_lot@autograf.pl> wrote in message news:bjp48k$npk$1@atlantis.news.tpi.pl...

for these 3 port maps you need additional signal + signal assignment
A => X and Y, --
relation and relation
B => not (X xor Y), -- not
(relation and relation)
F => '0' & Q(14 downto 0), --
aggregate

for example A => X_and_Y, (assignment: X_and_Y <= X and Y; )

this one should works - this is static expression
E => x"430F", --
literal

the two following should works - this is function conversion - first on
actual, second on formal
C => std_logic(Y), --
function_call(actual_designator)
std_logic(D) => Z -- case
of a function call on the formal part for an output port


Would be nice if VHDL has similar to Verilog behaviour in such cases
(such process is implicitly generated by simulator).

regards,
MK.


"eadgbe" <idont@thinkso.com> wrote in message
news:Wbudnfj3dfsPe8KiU-KYuA@comcast.com...
I have a test case below that fails to compile in Modelsim. The issue
revolves around
the use of expressions for actuals. Modelsim and I are at odds over the
legality
of the syntax below. I've run the following code in Synplicity and
Synopsys, and it
compiles and synthesizes successfully in both. If anyone out there has
access to
any other tools to compile and/or synthesize this code, I'd appreciate the
help. I need
ammo before I blast Mentor any further. Arguing the LRM is getting me
nowhere.

I'll post my final results after I get this resolved.

Thanks, in advance,

Bob Luking


-- start of test case --

library ieee;
use ieee.std_logic_1164.all;

entity A is
port
(
A : in std_logic;
B : in std_logic;
C : in std_logic;
E : in std_logic_vector(15 downto 0);
F : in std_logic_vector(15 downto 0);

D : out std_logic
);
end A;

architecture rtl of A is
begin
D <= A xor B xor C xor E(0) xor F(0);
end rtl;

---------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;

entity Test is
port
(
X : in std_logic;
Y : in std_logic;
Q : in std_logic_vector(15 downto 0);

Z : out std_logic
);
end Test;

architecture RTL of Test is

component A is
port
(
A : in std_logic;
B : in std_logic;
C : in std_logic;
E : in std_logic_vector(15 downto 0);
F : in std_logic_vector(15 downto 0);

D : out std_logic
);
end component;

begin

U0 : A
port map
(
A => X and Y, --
relation and relation
B => not (X xor Y), -- not
(relation and relation)
C => std_logic(Y), --
function_call(actual_designator)
E => x"430F", --
literal
F => '0' & Q(14 downto 0), --
aggregate

std_logic(D) => Z -- case
of a function call on the formal part for an output port
);

end RTL;

-- end of test case --