Tool for converting Schematic Entry To HDL

[benn]

Does a tool exist that can take a design done in Altera's schematic
entry, for example, and convert it to Verilog code?

Thanks!

 

[gabor]

On Mar 15, 2:18 pm, benn <benn...@hotmail.com> wrote:

Does a tool exist that can take a design done in Altera's schematic
entry, for example, and convert it to Verilog code?

Thanks!

The old Aldec-based schematic editor in early Xilinx Foundation
(up to 4.1i) had a translation feature, but it went to VHDL, not
Verilog. Most schematic entry programs use a proprietary file
format, so you'd have to ask if your schematics vendor has the
utility you need.

By the way, when translating from schematic to HDL, you generally
get a bunch of structural code (lots of instantiations and no
equations), so this may not really do what you wanted anyway.

Regards,
Gabor

 

[mjl296@hotmail.com]

On 15 Mar, 18:18, benn <benn...@hotmail.com> wrote:

Does a tool exist that can take a design done in Altera's schematic
entry, for example,  and convert it to Verilog code?

Thanks!

You can save Altera BDF schematics as Verilog (or VHDL)...

With the schematic open in Quartus II, select: "File->Create/Update-

"Create HDL Design File for Current File"

I'm using Quartus 7.2, but I seem to recall this option has been in
Quartus for years.

 

[benn]

On Mar 17, 7:05 am, "mjl...@hotmail.com" <mjl...@hotmail.com> wrote:

On 15 Mar, 18:18, benn <benn...@hotmail.com> wrote:

Does a tool exist that can take a design done in Altera's schematic
entry, for example, and convert it to Verilog code?

Thanks!

You can save Altera BDF schematics as Verilog (or VHDL)...

With the schematic open in Quartus II, select: "File->Create/Update-

"Create HDL Design File for Current File"

I'm using Quartus 7.2, but I seem to recall this option has been in
Quartus for years.

Thanks, Im using 7.2 as well, however maybe its something to do with
my file, but that "Create AHDL file for Current File" option just
creates a function .inc file lists all the inputs net names and
outputs nets of the block. The actual logic within the .gdf isn't
converted.

On a side note, I tried just to compile the gdf (schematic entry) file
as-is, with Quartus 7.2 and it fails because of missing LPM
dependencies. I thought Quartus 7.2 was backward compatible with
Max Plus II and contains all the old macro library functions... is
that not true? Do I perhaps need to install or enable some legacy
max plus package for Quartus?

Thanks!

 

On Mar 18, 6:51 pm, benn <benn...@hotmail.com> wrote:

On Mar 17, 7:05 am, "mjl...@hotmail.com" <mjl...@hotmail.com> wrote:

On 15 Mar, 18:18, benn <benn...@hotmail.com> wrote:

Does a tool exist that can take a design done in Altera's schematic
entry, for example, and convert it to Verilog code?

Thanks!

You can save Altera BDF schematics as Verilog (or VHDL)...

With the schematic open in Quartus II, select: "File->Create/Update-

"Create HDL Design File for Current File"

I'm using Quartus 7.2, but I seem to recall this option has been in
Quartus for years.

Thanks, Im using 7.2 as well, however maybe its something to do with
my file, but that "Create AHDL file for Current File" option just
creates a function .inc file lists all the inputs net names and
outputs nets of the block. The actual logic within the .gdf isn't
converted.

On a side note, I tried just to compile the gdf (schematic entry) file
as-is, with Quartus 7.2 and it fails because of missing LPM
dependencies. I thought Quartus 7.2 was backward compatible with
Max Plus II and contains all the old macro library functions... is
that not true? Do I perhaps need to install or enable some legacy
max plus package for Quartus?

Thanks!

I am using Quartus 7.2, actually, you can create both AHDL and HDL
file. for the HDL file, you can create either verilog and VHDL file.
so nice Quartus.

Rotor