Tool for connecting modules,download free,quick demo

[Song]

Topweaver v2.0
A GUI-based tool for connecting HDL modules, also called structural
integration. You can use it in ASIC, FPGA or CPLD designs.

FEATURES
Extract ports from cell modules automatically
Full mixed Verilog, Verilog 2001 and VHDL supported
Automatically language recognition
Connect ports in graph interface
Great visual aid while connecting
Smart Link technology enable you to connect ports automatically
Bus combination and inout construction
Generate Verilog/VHDL connection module automatically
Output detailed module summary in HTML format
Output formatted file list
DelayGen
...

Homepage: http://www.topweaver.com
Download: http://www.topweaver.com/download.htm
Quick Demo: http://www.topweaver.com/demo.htm

Topweaver.com

 

[wkong]

Why doesnt it provide a Linux Version.
We all use Linux or Unix.
Use Verilog-mode also can do such things.
"Song" <songtn@vip.sina.com>
??????:aec7dd9e.0311170727.1c8a657@posting.google.com...

Topweaver v2.0
A GUI-based tool for connecting HDL modules, also called structural
integration. You can use it in ASIC, FPGA or CPLD designs.

FEATURES
Extract ports from cell modules automatically
Full mixed Verilog, Verilog 2001 and VHDL supported
Automatically language recognition
Connect ports in graph interface
Great visual aid while connecting
Smart Link technology enable you to connect ports automatically
Bus combination and inout construction
Generate Verilog/VHDL connection module automatically
Output detailed module summary in HTML format
Output formatted file list
DelayGen
...

Homepage: http://www.topweaver.com
Download: http://www.topweaver.com/download.htm
Quick Demo: http://www.topweaver.com/demo.htm

Topweaver.com

 

[Song]

Hello,

Why doesnt it provide a Linux Version.
I would like to write a Linux/Solaris version of Topweaver if such a

development is needed and accepted. As I have known, the famous tool-
Active HDL also has only Windows version. At present, maybe you can
use Topweaver on a linux platform with Wine. I have seen many Windows
programs run on linux with Wine. For details, you can visit
http://www.winehq.com .

We all use Linux or Unix.
Many people here, including me, use Unix for developing. But I think

maybe some work can be done more conveniently on Windows. So, usually
there are a few Windows machines in the lab.

Use Verilog-mode also can do such things.
Would you please say more clearly of your "Verilog-mode"? I have

tested many relational tools. All of them need at least ten minutes to
finish the work shown in the demo
page(http://www.topweaver.com/demo.htm). With Topweaver, I use 50
seconds, without any error.

Regards

"wkong" <wkong@xinhuanet.com> wrote in message news:<bpp72l$2opj$1@mail.cn99.com>...

Why doesnt it provide a Linux Version.
We all use Linux or Unix.
Use Verilog-mode also can do such things.
"Song" <songtn@vip.sina.com
??????:aec7dd9e.0311170727.1c8a657@posting.google.com...
Topweaver v2.0
A GUI-based tool for connecting HDL modules, also called structural
integration. You can use it in ASIC, FPGA or CPLD designs.

FEATURES
Extract ports from cell modules automatically
Full mixed Verilog, Verilog 2001 and VHDL supported
Automatically language recognition
Connect ports in graph interface
Great visual aid while connecting
Smart Link technology enable you to connect ports automatically
Bus combination and inout construction
Generate Verilog/VHDL connection module automatically
Output detailed module summary in HTML format
Output formatted file list
DelayGen
...

Homepage: http://www.topweaver.com
Download: http://www.topweaver.com/download.htm
Quick Demo: http://www.topweaver.com/demo.htm

Topweaver.com

 

[Rudolf Usselmann]

songtn@vip.sina.com (Song) wrote in message news:<aec7dd9e.0311170727.1c8a657@posting.google.com>...

Topweaver v2.0
A GUI-based tool for connecting HDL modules, also called structural
integration. You can use it in ASIC, FPGA or CPLD designs.

FEATURES
Extract ports from cell modules automatically
Full mixed Verilog, Verilog 2001 and VHDL supported
Automatically language recognition
Connect ports in graph interface
Great visual aid while connecting
Smart Link technology enable you to connect ports automatically
Bus combination and inout construction
Generate Verilog/VHDL connection module automatically
Output detailed module summary in HTML format
Output formatted file list
DelayGen
...

Homepage: http://www.topweaver.com
Download: http://www.topweaver.com/download.htm
Quick Demo: http://www.topweaver.com/demo.htm

Topweaver.com

A similar tool, but without the graphical user interface can
be freely downloaded from www.asics.ws. It's written in perl,
and release under GPL. Since it is provided as a perl script,
it will run on any platform perl will run.

It can be found on the "Free Tools" page.

Best Regards,
rudi
========================================================
ASICS.ws ::: Solutions for your ASIC/FPGA needs :::
...............::: FPGAs * Full Custom ICs * IP Cores :::
FREE IP Cores -> http://www.asics.ws/ <- FREE EDA Tools

 

[wkong]

Hello
verilog-mode is writen by Wilson Snyder in Elisp language used in
Emacs, I found it is very useful, can auto instance pre-writen modules, and
can auto complete sensetive list etc. Please refer to
http://www.veripool.com/verilog-mode.html
I use it in my all verilog source coding works.
"Song" <songtn@vip.sina.com> wrote in message
news:aec7dd9e.0311240608.13c604e7@posting.google.com...

Hello,
Why doesnt it provide a Linux Version.
I would like to write a Linux/Solaris version of Topweaver if such a
development is needed and accepted. As I have known, the famous tool-
Active HDL also has only Windows version. At present, maybe you can
use Topweaver on a linux platform with Wine. I have seen many Windows
programs run on linux with Wine. For details, you can visit
http://www.winehq.com .
We all use Linux or Unix.
Many people here, including me, use Unix for developing. But I think
maybe some work can be done more conveniently on Windows. So, usually
there are a few Windows machines in the lab.
Use Verilog-mode also can do such things.
Would you please say more clearly of your "Verilog-mode"? I have
tested many relational tools. All of them need at least ten minutes to
finish the work shown in the demo
page(http://www.topweaver.com/demo.htm). With Topweaver, I use 50
seconds, without any error.

Regards

"wkong" <wkong@xinhuanet.com> wrote in message
news:<bpp72l$2opj$1@mail.cn99.com>...
Why doesnt it provide a Linux Version.
We all use Linux or Unix.
Use Verilog-mode also can do such things.
"Song" <songtn@vip.sina.com
??????:aec7dd9e.0311170727.1c8a657@posting.google.com...
Topweaver v2.0
A GUI-based tool for connecting HDL modules, also called structural
integration. You can use it in ASIC, FPGA or CPLD designs.

FEATURES
Extract ports from cell modules automatically
Full mixed Verilog, Verilog 2001 and VHDL supported
Automatically language recognition
Connect ports in graph interface
Great visual aid while connecting
Smart Link technology enable you to connect ports automatically
Bus combination and inout construction
Generate Verilog/VHDL connection module automatically
Output detailed module summary in HTML format
Output formatted file list
DelayGen
...

Homepage: http://www.topweaver.com
Download: http://www.topweaver.com/download.htm
Quick Demo: http://www.topweaver.com/demo.htm

Topweaver.com

 

[Song]

Hi,
Thanks for your reading. Now I am thinking if my English is too poor
to express what Topweaver is.
I should say that the functions you mentioned in your current tools
are too simple to say in Topweaver.

A similar tool, but without the graphical user interface can
be freely downloaded from www.asics.ws. It's written in perl,
and release under GPL. Since it is provided as a perl script,
it will run on any platform perl will run.
The graphical user interface is the most important feature of

Topweaver, which takes most of the total codes.
The development of Topweaver is very formal. The programer has more
than ten years' software experience and more than three years'
FPGA/ASIC experience. More than 50 real Topweaver projects have been
tested, including the large project having more than 1000 ports.
I have tried to use your mentioned tool(Topgen). I use a few testcases
from Topweaver's to test. I think the following code generated by
Topgen is not correct:
wire \clk--+a;
....
.\clk--+a( \clk--+a ),
The space is missing.
Most important, such tool just generate a framework. I should still do
a lot of text editing work. Topweaver can generate the FULL connection
codes without a keyboard!

verilog-mode is writen by Wilson Snyder in Elisp language used in
Emacs, I found it is very useful, can auto instance pre-writen modules, and
can auto complete sensetive list etc. Please refer to
http://www.veripool.com/verilog-mode.html
I use it in my all verilog source coding works.
I have visited this web site. In fact, many of the similar topics have

been read before/during the development of Topweaver.
Some of the contents that page mentioned are already old. For example,
now verilog 2001 can parse such codes:
module ma(
input rst,
input clock,
...
Verilog 2001 is now supported by most EDA tools, including Topweaver.
About the topic instantiations, which is our concerned, I think they
are different. "Most important, such tool just generate a framework. I
should still do a lot of text editing work. Topweaver can generate the
FULL connection codes without a keyboard!"

I hope this answers your questions. If I can be of any other
assistance, please let me know. Additionally, would you please answer
these questions before your ask?
1. Have you visited http://www.topweaver.com/demo.htm to know what
topweaver is?
2. To finish such a demo project, using Topweaver, I spend 50 seconds,
without any error. What is your record by your current tool?

Regards

 

[Andrew Mazin]

Topweaver can generate the FULL connection
codes without a keyboard!

Keyboard-less ASIC design is usually followed by verification nightmare...

-Andrew

 

[wkong]

Song:
I've browsed the topweaver homepage and the demo, I feel it
indeed a good tool, and can save much time. If the parameter limitation of
verilog recognition was fixed, I think it will do more favor. I use the
parameter much frequently.
I suggest that if you port it into linux, more and more IC
designers will use it whenever they are integration there modules including
me.
Maybe you can also provide a testbench framework for the
generated topmodule as well. Because every topmodule should be tested. I
imagine a verilog wave generator(with auxiliary wave description files) will
come out into being.
Thank you, I'm a digital designer with one and a half years of
ASIC experience. I hope to be a friend of you. I hope I can do a little
favor for you incoming project. I love asic design and linux.
Thank you again!

wkong@xinhuanet.com
"Song" <songtn@vip.sina.com> wrote in message
news:aec7dd9e.0312100859.694842cb@posting.google.com...

Hi,
Thanks for your reading. Now I am thinking if my English is too poor
to express what Topweaver is.
I should say that the functions you mentioned in your current tools
are too simple to say in Topweaver.

A similar tool, but without the graphical user interface can
be freely downloaded from www.asics.ws. It's written in perl,
and release under GPL. Since it is provided as a perl script,
it will run on any platform perl will run.
The graphical user interface is the most important feature of
Topweaver, which takes most of the total codes.
The development of Topweaver is very formal. The programer has more
than ten years' software experience and more than three years'
FPGA/ASIC experience. More than 50 real Topweaver projects have been
tested, including the large project having more than 1000 ports.
I have tried to use your mentioned tool(Topgen). I use a few testcases
from Topweaver's to test. I think the following code generated by
Topgen is not correct:
wire \clk--+a;
...
.\clk--+a( \clk--+a ),
The space is missing.
Most important, such tool just generate a framework. I should still do
a lot of text editing work. Topweaver can generate the FULL connection
codes without a keyboard!



verilog-mode is writen by Wilson Snyder in Elisp language used in
Emacs, I found it is very useful, can auto instance pre-writen modules,
and
can auto complete sensetive list etc. Please refer to
http://www.veripool.com/verilog-mode.html
I use it in my all verilog source coding works.
I have visited this web site. In fact, many of the similar topics have
been read before/during the development of Topweaver.
Some of the contents that page mentioned are already old. For example,
now verilog 2001 can parse such codes:
module ma(
input rst,
input clock,
...
Verilog 2001 is now supported by most EDA tools, including Topweaver.
About the topic instantiations, which is our concerned, I think they
are different. "Most important, such tool just generate a framework. I
should still do a lot of text editing work. Topweaver can generate the
FULL connection codes without a keyboard!"

I hope this answers your questions. If I can be of any other
assistance, please let me know. Additionally, would you please answer
these questions before your ask?
1. Have you visited http://www.topweaver.com/demo.htm to know what
topweaver is?
2. To finish such a demo project, using Topweaver, I spend 50 seconds,
without any error. What is your record by your current tool?

Regards

 

[Song]

Hi wkong,

I've browsed the topweaver homepage and the demo, I feel it
indeed a good tool, and can save much time.
I am glad you know what Topweaver is. I appreciate your help if you

can recommend Topweaver to others.

If the parameter limitation of
verilog recognition was fixed, I think it will do more favor. I use the
parameter much frequently.
This function will be added in the future version. Now you can modify

the output HDL code to add the ignored ports.

I suggest that if you port it into linux, more and more IC
designers will use it whenever they are integration there modules including
me.
According to my last message, I think you can already use Topweaver

v2.0 on linux with the help of Wine, which is a dedault tool of
Redhat. Maybe a future version of Topweaver will be natively built on
Linux, if it is needed. If you need Topweaver, you need not to wait to
the future version, because you can only pay the difference to buy the
future version. You can see details when you register.

Maybe you can also provide a testbench framework for the
generated topmodule as well. Because every topmodule should be tested. I
imagine a verilog wave generator(with auxiliary wave description files) will
come out into being.
There are already many tools having such functions. For example,

Xilinx ISE. In fact, Topweaver can also generate such a framework: New
a poject with the wanted file(s), generate the output HDL. Because you
can generate the result at any time. The difference from other tools
is only without reg declarations. HDL bencher in ISE can generate
testbench from drawing wave.

Thank you, I'm a digital designer with one and a half years of
ASIC experience. I hope to be a friend of you.
You are welcome!

I hope I can do a little
favor for you incoming project.
I can not grasp this sentence.

I love asic design and linux.
Thank you again!

wkong@xinhuanet.com
Thank you very much.

Regards
Topweaver.com

 

[Song]

Hi,

Topweaver can generate the FULL connection
codes without a keyboard!

Keyboard-less ASIC design is usually followed by verification nightmare...

-Andrew
I can understand your feeling, but I want to say:

1, "Topweaver can generate the FULL connection codes without a
keyboard" does NOT equal to "You can not use a keyboard". The total
procedure is totally controlled. You can know this by visiting
http://www.topweaver.com . You can also modify the output HDL codes,
which is very easy to read.
2, Why we need verification? Because the DUT(Design under test) is
written by human beings. When a man write 100 lines codes, the
probability of existing errors is greater than 70%; When he write 500
lines codes, the probability of existing errors is greater than 98%;
When he write 1000 lines codes, the probability of existing errors is
greater than 99.99%. Automatization is tested to be a good way to
reduce errors.
Topweaver is a formal tool. The first version is released in May 2002.
The zipped install file is 6.35MB. I wish you can spend a little time
in learning what Topweaver is. At least, would you please watch a 4
minutes' flash demo movie by just a clicking at
http://www.topweaver.com/demo.htm ?

Homepage: http://www.topweaver.com
Free Download: http://www.topweaver.com/download.htm
Quick Demo: http://www.topweaver.com/demo.htm

Regards