Too many signals [Xilinx Foundation 4.1i]

[Basuki Endah Priyanto]

Hi all,
I'd like to highlight a problem encountered while using the Xilinx foundation series 4.1i. I am unable to connect all the input ports to the respective output ports due the following comments shown:
Too many signals: Checking for sourceless, loadless nets and multiple drivers aborted.
I suspect that there is a limit to the number of bus terminal labels that we can give on a schematic.
The bus terminal labels are given to the inputs and outputs ports so that they need not to be physically connected with wires. These termianl labels are essential as it is impossible to physically connect the ports together with wires under the constraint of the space given in the schematic.

Any idea how to solve the problem ???


Thanks.

Buzz

 

[lnguyen]

Hi, <p>That sounds interesting since I've never seen such error message. Sourceless and loadless are okay, but multiple drivers will cause error. Try double check you circuit and possibply break it into macros levels if it's too big.

 

[lnguyen]

Hi, <p>That sounds interesting since I've never seen such error message. Loadless are okay, but multiple drivers and loadless gate will cause error. Try double check you circuit and possibply break it into macros levels if it's too big.

 

[lnguyen]

hi, that sounds interesting since I've not seen such error before. Loadless is okay but sourceless and multiple drive will cause unexpected error, sometimes the software will gives up and post some silly message. Check your circuit and possibly break it into smaller macros blocks thst may help. <p>good luck,

 

[Colm Clancy]

If I remember right this was a known issue way back where the number of signals on a sheet could not exceed 1024. The workaround was (as lnguyen) said to split the design over multiple sheets

Basuki Endah Priyanto wrote:

Hi all,
I'd like to highlight a problem encountered while using the Xilinx foundation series 4.1i. I am unable to connect all the input ports to the respective output ports due the following comments shown:
Too many signals: Checking for sourceless, loadless nets and multiple drivers aborted.
I suspect that there is a limit to the number of bus terminal labels that we can give on a schematic.
The bus terminal labels are given to the inputs and outputs ports so that they need not to be physically connected with wires. These termianl labels are essential as it is impossible to physically connect the ports together with wires under the constraint of the space given in the schematic.

Any idea how to solve the problem ???

Thanks.

Buzz

 

[Basuki Endah Priyanto]

Hi,

many thanks for ur suggestionz, it works !

-----Original Message-----
From: Colm Clancy [mailto:colmc@xilinx.com]
Posted At: Wednesday, December 10, 2003 2:16 AM
Posted To: fpga
Conversation: Too many signals [Xilinx Foundation 4.1i]
Subject: Re: Too many signals [Xilinx Foundation 4.1i]


If I remember right this was a known issue way back where the number of signals on a sheet could not exceed 1024. The workaround was (as lnguyen) said to split the design over multiple sheets

Basuki Endah Priyanto wrote:

Hi all,
I'd like to highlight a problem encountered while using the Xilinx foundation series 4.1i. I am unable to connect all the input ports to the respective output ports due the following comments shown:
Too many signals: Checking for sourceless, loadless nets and multiple drivers aborted.
I suspect that there is a limit to the number of bus terminal labels that we can give on a schematic.
The bus terminal labels are given to the inputs and outputs ports so that they need not to be physically connected with wires. These termianl labels are essential as it is impossible to physically connect the ports together with wires under the constraint of the space given in the schematic.

Any idea how to solve the problem ???

Thanks.

Buzz