to_unsigned as an expression in an aggregate

[Nick Bayard]

I'm getting some odd results when I try to use an aggregate expression to pack several unsigned vectors. I get the error. "This expression must be of a locally static subtype. Invalid aggregate." If I use the concatenate operator (commented below), it seems to compile file. Is this bug from my vendor tool (Aldec) or is there some reason I can't use to_unsigned in an aggregate? Thanks.


library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

entity my_entity is
port
(
output : out unsigned(39 downto 0)
);
end;

architecture my_arch of my_entity is
signal int1 : integer := 0;
signal int2 : integer := 0;
signal us1 : unsigned(9 downto 0) := (others => '0');
signal us2 : unsigned(9 downto 0) := (others => '0');
begin
output <= (to_unsigned(int1,10), to_unsigned(int2,10), us1, us2);
--output <= to_unsigned(int1,10) & to_unsigned(int2,10) & us1 & us2;
end;

 

[Brian Drummond]

On Fri, 22 Feb 2013 12:50:38 -0800, Nick Bayard wrote:

I'm getting some odd results when I try to use an aggregate expression
to pack several unsigned vectors. I get the error. "This expression
must be of a locally static subtype. Invalid aggregate."

port (

output : out unsigned(39 downto 0)
);

A 40-bit unsigned.

output <= (to_unsigned(int1,10), to_unsigned(int2,10), us1, us2);
--output <= to_unsigned(int1,10) & to_unsigned(int2,10) & us1 & us2;

One of these generates a 40-bit unsigned; the other generates an array of
four 10-bit unsigneds.

I would only expect the one that matches the actual port type to work.

- Brian

 

[Andy]

The VHDL-2008 standard was updated to addresses this, but I don't know whether it requires named vs positional notation in the aggregate expression for this to be allowed. I also don't know if the size of the actual must be locally static (e.g. whether a call to to_unsigned() would work), but that may be taken care of by named association.

output <= (39 downto 30 => to_unsigned(int1,10),
29 downto 20 => to_unsigned(int2,10),
19 downto 10 => us1,
9 downto 0 => us2);

This also depends on whether your tool supports VHDL-2008.

Support for 2008 is an option that must be enabled for the tool, and then there may be (most likely are) limitations as to which new-for-2008 features are supported.

Another really nice change is that std_logic_vector is now a resolved subtype of std_ulogic_vector. Which means these two formerly separate types can now be direclty assigned to and/or associated with each other without explicit conversion.

Andy

 

[Nick Bayard]

On Friday, February 22, 2013 5:11:09 PM UTC-6, Brian Drummond wrote:

One of these generates a 40-bit unsigned; the other generates an array of

four 10-bit unsigneds.



I would only expect the one that matches the actual port type to work.



- Brian

Thanks Brian. This the first time that I've heard anyone mention anything indicating that these two expressions did anything differently.

 

[Nick Bayard]

On Monday, February 25, 2013 4:14:45 PM UTC-6, Andy wrote:

This also depends on whether your tool supports VHDL-2008.



Support for 2008 is an option that must be enabled for the tool, and then there may be (most likely are) limitations as to which new-for-2008 features are supported.

Andy

Andy, my tool does claim to support VHDL-2008 and it is enabled. At this point, the error appears to lie somewhere between my incorrect implementation and the incorrect implementation of the tool. Thanks.

 

[Andy]

On Tuesday, February 26, 2013 6:56:40 AM UTC-6, Nick Bayard wrote:

On Monday, February 25, 2013 4:14:45 PM UTC-6, Andy wrote: > This also depends on whether your tool supports VHDL-2008. > > > > Support for 2008 is an option that must be enabled for the tool, and then there may be (most likely are) limitations as to which new-for-2008 features are supported. > > Andy Andy, my tool does claim to support VHDL-2008 and it is enabled. At this point, the error appears to lie somewhere between my incorrect implementation and the incorrect implementation of the tool. Thanks.

Did you try named association instead of positional association in the aggregate expression? Check your tool user manual to see what parts of 2008 they support.

Andy

 

[HT-Lab]

On 22/02/2013 20:50, Nick Bayard wrote:

I'm getting some odd results when I try to use an aggregate expression to pack several unsigned vectors. I get the error. "This expression must be of a locally static subtype. Invalid aggregate." If I use the concatenate operator (commented below), it seems to compile file. Is this bug from my vendor tool (Aldec) or is there some reason I can't use to_unsigned in an aggregate? Thanks.


library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

entity my_entity is
port
(
output : out unsigned(39 downto 0)
);
end;

architecture my_arch of my_entity is
signal int1 : integer := 0;
signal int2 : integer := 0;
signal us1 : unsigned(9 downto 0) := (others => '0');
signal us2 : unsigned(9 downto 0) := (others => '0');
begin
output <= (to_unsigned(int1,10), to_unsigned(int2,10), us1, us2);
--output <= to_unsigned(int1,10) & to_unsigned(int2,10) & us1 & us2;
end;

Works fine in Modelsim (10.2)

Hans
www.ht-lab.com

 

[nbayard]

On Wednesday, February 27, 2013 3:30:48 AM UTC-6, HT-Lab wrote:

Works fine in Modelsim (10.2)



Hans

www.ht-lab.com

Aldec has acknowledged that it was a problem with the tool.