to wire, or not to wire

[Mahurshi Akilla]

i guess this is another basic question. it
is bugging me out. it is about when to (and
maybe when not to) use a wire.

i have the following code:

module wire_nowire(a, b);
input a;
output b;

wire a;
wire b;

assign b = ~a;

endmodule

i simulated the above and i get b = ~a, which is good.

i still get the same output even if i comment out
wire a, or wire b, or both wire a and wire b.

so when should (and shouldn't) a wire be used anyway?

Mahurshi Akilla

 

If a and b are not in port list, you have to define them as wire.

Nandy
www.nandigits.com
Netlist Debug/ECO in GUI mode

 

[Ralf Hildebrandt]

Mahurshi Akilla wrote:

module wire_nowire(a, b);
input a;
output b;

wire a;
wire b;

assign b = ~a;

endmodule

i still get the same output even if i comment out
wire a, or wire b, or both wire a and wire b.

Type wire is implicitly given to any signal, that is not declared
otherwise. Verilog is (unfortunately) not a strongly typed language.

Ralf

 

[Petter Gustad]

Ralf Hildebrandt <Ralf-Hildebrandt@gmx.de> writes:

Type wire is implicitly given to any signal, that is not declared
otherwise.

Unless you specify (Verilog2001):

`default_nettype none

Petter
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