D
DW
Guest
Hello,
I'm using Altera Quartus 2 to produce FPGA based designs. My question is
whether I should infer memory arrays in my modules (which I think I prefer
to do because it seems natural to do so and it seems to work OK so far) or
to use the wizard to create separate memory modules and then call these up
in my Verilog code.
I'm sure there are pro's and con's but would be interested to hear from
anyone with relevant experience and advice.
Thanks,
DW
I'm using Altera Quartus 2 to produce FPGA based designs. My question is
whether I should infer memory arrays in my modules (which I think I prefer
to do because it seems natural to do so and it seems to work OK so far) or
to use the wizard to create separate memory modules and then call these up
in my Verilog code.
I'm sure there are pro's and con's but would be interested to hear from
anyone with relevant experience and advice.
Thanks,
DW