to generate random numbers using verilog-A

[vicky]

hi friends,

i am new to this forum. i am working on cadence and i dont know how
to generate random numbers using verilog-A. can anyone help me in
this case.

bye

 

[Bernd Fischer]

RFTM, sorry but this is pretty well documented.

Generating Random Numbers
Cadence Verilog-A Language Reference,
Chapter 9, Simulator Functions

Bernd

vicky wrote:

hi friends,

i am new to this forum. i am working on cadence and i dont know how
to generate random numbers using verilog-A. can anyone help me in
this case.

bye

 

[Bernd Fischer]

There is even an implementation example in
the Cadence sample library 'ahdlLib', cell 'rand_bit_stream'
which you can find under
<installDir>/tools/dfII/samples/artist

Bernd

vicky wrote:

hi friends,

i am new to this forum. i am working on cadence and i dont know how
to generate random numbers using verilog-A. can anyone help me in
this case.

bye