To comment if it's a good style

[¤T¤HŚćĽ˛Śł§ÚŽv]

Dear all,
I'm confused when studying the textbook-Digital Logic with VHDL Design.

The question-5.17 in chapter 5.
Given the relation between input and output.
And Knowing the function of the circuit,
what's the point should I notice to judge if the code is good or not ?
So far, I take the code's functionality as a MUX.
A little bit strange...
I appreciate for any suggestion .
----------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all

ENTITY problem IS
PORT (Input : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
Output : OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END problem;

ARCHITECTURE LogicFunc OF problem IS
BEGIN
WITH Input SELECT
Output <="0001" WHEN "0101",
"0010" WHEN "0110",
"0011" WHEN "0111",
"0010" WHEN "1001",
"0100" WHEN "1010",
"0110" WHEN "1011",
"0011" WHEN "1101",
"0110" WHEN "1110",
"1001" WHEN "1111",
"0000" WHEN OTHERS,
END LogicFunc;
--
 Ą°ľoŤHŻ¸: ş~ŻŤ¤pŻ¸ <bbs.ee.nsysu.edu.tw>
 Ąť From: pailiou.ee.nsysu.edu.tw

 

[@see.my.sig>]

??????? wrote:

Dear all,
I'm confused when studying the textbook-Digital Logic with VHDL Design.

The question-5.17 in chapter 5.
Given the relation between input and output.
And Knowing the function of the circuit,
what's the point should I notice to judge if the code is good or not ?
So far, I take the code's functionality as a MUX.
A little bit strange...
I appreciate for any suggestion .

It's legal VHDL, the concurrent form of the 'case' statement.

Not really a MUX though. It maps the input vector through to the output:

input map to output
0,1,2,3 0,0,0,0
4,5,6,7 0,1,2,3
8,9,A,B 0,2,4,6
C,D,E,F 0,3,6,9

- a sort of sequence generator?

----------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all

ENTITY problem IS
PORT (Input : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
Output : OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END problem;

ARCHITECTURE LogicFunc OF problem IS
BEGIN
WITH Input SELECT
Output <="0001" WHEN "0101",
"0010" WHEN "0110",
"0011" WHEN "0111",
"0010" WHEN "1001",
"0100" WHEN "1010",
"0110" WHEN "1011",
"0011" WHEN "1101",
"0110" WHEN "1110",
"1001" WHEN "1111",
"0000" WHEN OTHERS,
END LogicFunc;
--
 ????: ???? <bbs.ee.nsysu.edu.tw>
 ? From: pailiou.ee.nsysu.edu.tw

--

Regards,

Brent Hayhoe.

Aftonroy Limited Telephone: +44 (0)20-8449-1852
135 Lancaster Road,
New Barnet, Mobile: +44 (0)7966-472574
Herts., EN4 8AJ, U.K. Email: <A
HREF="mailto:&#066;&#114;&#101;&#110;&#116;&#046;&#072;&#097;&#121;&#104;&#111;&#101;&#064;&#065;&#102;&#116;&#111;&#110;&#114;&#111;&#121;&#046;&#099;&#111;&#109;">

 

[A123b456c]

Subject: To comment if it's a good style
From: pailiou.bbs@bbs.ee.nsysu.edu.tw (¤T¤HŚćĽ˛Śł§ÚŽv)
Date: 11/7/03 2:15 AM US
Message-id: &lt;49AgkB$41U@bbs.ee.nsysu.edu.tw

Dear all,
I'm confused when studying the textbook-Digital Logic with VHDL Design.

The question-5.17 in chapter 5.
Given the relation between input and output.
And Knowing the function of the circuit,
what's the point should I notice to judge if the code is good or not ?
So far, I take the code's functionality as a MUX.
A little bit strange...
I appreciate for any suggestion .
----------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all

ENTITY problem IS
PORT (Input : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
Output : OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END problem;

ARCHITECTURE LogicFunc OF problem IS
BEGIN
WITH Input SELECT
Output &lt;="0001" WHEN "0101",
"0010" WHEN "0110",
"0011" WHEN "0111",
"0010" WHEN "1001",
"0100" WHEN "1010",
"0110" WHEN "1011",
"0011" WHEN "1101",
"0110" WHEN "1110",
"1001" WHEN "1111",
"0000" WHEN OTHERS,
END LogicFunc;
--
 :  &lt;bbs.ee.nsysu.edu.tw&gt;
 From: pailiou.ee.nsysu.edu.tw






This is not a mux. A mux is a combinational (no flip flops) circuit that has

at least 2 data inputs of (theoretically) any bit length and a control input
the bit length of which is the dual logarithm of the number of the data inputs.
It also has an output
the bit length of which is equal to the bit length of the data inputs.
Your code doesn't model a mux. It simply
maps (translates if you will) a bit sequence to another. You can call it a
decoder if you want.
And what do you mean by "good style"??
Your code correctly describes some piece of hardware. It 'll simulate correctly
and it will alsol synthesize correctly to some piece of hardware. Now, if THAT
hardware
was your intention, well, that's another story.
And please take the advise of an old veteran:
Learn what's hardwatre first.
Then, learn how to design it.
And last, learn how to model it using hardware description language(s).
But if you insist on starting at the end, you
must go to Verilog. It causes less nightmares.

 

[Jim Lewis]

A123b456c wrote:

LIBRARY ieee;
USE ieee.std_logic_1164.all

ENTITY problem IS
PORT (Input : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
Output : OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END problem;

ARCHITECTURE LogicFunc OF problem IS
BEGIN
WITH Input SELECT
Output &lt;="0001" WHEN "0101",
"0010" WHEN "0110",
"0011" WHEN "0111",
"0010" WHEN "1001",
"0100" WHEN "1010",
"0110" WHEN "1011",
"0011" WHEN "1101",
"0110" WHEN "1110",
"1001" WHEN "1111",
"0000" WHEN OTHERS,
END LogicFunc;

You can think of this as either a truth table
or a very small ROM. This is a good coding style
for this type of hardware.

Start your design with a block diagram. Decompose
it into pieces you know how code. Examples of these
pieces are: Mux, Register, Statemachine, Adder,
Multiplier, simple logic, ...

But if you insist on starting at the end, you
must go to Verilog. It causes less nightmares.

Use Verilog? I would only give this advice to my competition.
The Verilog biggots are always yacking about how much more
compact it is and such. So for the above code, I would
ask them to show me a Verilog coding that uses
less statements than the above VHDL code. There isn't one.
In all of their code comparisons, they prefer to ignore
the existence of VHDL's concurrent statements

I would stick to VHDL as with Verilog there are lots
of ways to hang yourself and none of them
good (race conditions, dangling if statements, ...).

With VHDL, until you learn it, the compiler may
abuse you, but at least your logic will be closer
to functional once you get it into the simulator
(as if the compiler has a lint tool built in).

In your quest for learning VHDL, I have a number of
papers on my website you may wish to look at:
http://www.synthworks.com/papers

You will find the one on "Math Tricks" useful for
understanding VHDL's strong typing. Master this
and VHDL is easy.

Cheers,
Jim --
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Jim Lewis
Director of Training mailto:Jim@SynthWorks.com
SynthWorks Design Inc. http://www.SynthWorks.com
1-503-590-4787

Expert VHDL Training for Hardware Design and Verification
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

 

[Cameron, Charles B.]

@see.my.sig&gt; &gt; wrote:

??????? wrote:

Dear all,
I'm confused when studying the textbook-Digital Logic with VHDL Design.

The question-5.17 in chapter 5.
Given the relation between input and output.
And Knowing the function of the circuit,
what's the point should I notice to judge if the code is good or not ?
So far, I take the code's functionality as a MUX.
A little bit strange...
I appreciate for any suggestion .


It's legal VHDL, the concurrent form of the 'case' statement.

Not really a MUX though. It maps the input vector through to the output:

input map to output
0,1,2,3 0,0,0,0
4,5,6,7 0,1,2,3
8,9,A,B 0,2,4,6
C,D,E,F 0,3,6,9

- a sort of sequence generator?


----------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all

ENTITY problem IS
PORT (Input : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
Output : OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END problem;

ARCHITECTURE LogicFunc OF problem IS
BEGIN
WITH Input SELECT
Output &lt;="0001" WHEN "0101",
"0010" WHEN "0110",
"0011" WHEN "0111",
"0010" WHEN "1001",
"0100" WHEN "1010",
"0110" WHEN "1011",
"0011" WHEN "1101",
"0110" WHEN "1110",
"1001" WHEN "1111",
"0000" WHEN OTHERS,
END LogicFunc;


If you regard the input is consisting of two 2-bit numbers, then the

result is the 4-bit multiplicative product of those two numbers. In
other words, this function is a 2-bit by 2-bit multiplier. The style is
poor because this fact is not immediately evident. (At least, it is
poor if the intent was that this be a multiplier circuit.) Aside from
anything else, the total absence of comments in the code contributes to
its being so obscure. The use of binary strings instead of decimal
numbers doesn't contribute to the clarity of the code, either. Finally,
the name of the module is poorly selective. Why call it a LogicFunc
when it's really doing an arithmetic function?

Charles B. Cameron

 

[Brent Hayhoe]

Cameron, Charles B. wrote:

@see.my.sig&gt; &gt; wrote:
??????? wrote:

Dear all,
I'm confused when studying the textbook-Digital Logic with VHDL Design.

The question-5.17 in chapter 5.

Re. your comments about 'commenting' and 'style'; don't forget this appears to
be a problem/question set within a text book.

Good point though, I hadn't noticed the 2x2 multiplier in it.

&lt;snipped&gt;

If you regard the input is consisting of two 2-bit numbers, then the
result is the 4-bit multiplicative product of those two numbers. In
other words, this function is a 2-bit by 2-bit multiplier. The style is
poor because this fact is not immediately evident. (At least, it is
poor if the intent was that this be a multiplier circuit.) Aside from
anything else, the total absence of comments in the code contributes to
its being so obscure. The use of binary strings instead of decimal
numbers doesn't contribute to the clarity of the code, either. Finally,
the name of the module is poorly selective. Why call it a LogicFunc
when it's really doing an arithmetic function?

Charles B. Cameron

--

Regards,

Brent Hayhoe.

Aftonroy Limited
Email: <A
HREF="mailto:&#066;&#114;&#101;&#110;&#116;&#046;&#072;&#097;&#121;&#104;&#111;&#101;&#064;&#065;&#102;&#116;&#111;&#110;&#114;&#111;&#121;&#046;&#099;&#111;&#109;">

 

[Cameron, Charles B.]

Brent Hayhoe wrote:

Cameron, Charles B. wrote:

@see.my.sig&gt; &gt; wrote:

??????? wrote:

Dear all,
I'm confused when studying the textbook-Digital Logic with VHDL
Design.

The question-5.17 in chapter 5.


Re. your comments about 'commenting' and 'style'; don't forget this
appears to be a problem/question set within a text book.

Good point though, I hadn't noticed the 2x2 multiplier in it.

snipped

If you regard the input is consisting of two 2-bit numbers, then the
result is the 4-bit multiplicative product of those two numbers. In
other words, this function is a 2-bit by 2-bit multiplier. The style
is poor because this fact is not immediately evident. (At least, it
is poor if the intent was that this be a multiplier circuit.) Aside
from anything else, the total absence of comments in the code
contributes to its being so obscure. The use of binary strings
instead of decimal numbers doesn't contribute to the clarity of the
code, either. Finally, the name of the module is poorly selective.
Why call it a LogicFunc when it's really doing an arithmetic function?

Charles B. Cameron

Yes, it is from a very good textbook by Brown and Vranesic. The tenor

of the question has to do with critiquing the style and that's why the
author's used such poor style in it, so that students could consider how
obscure a design becomes when the style is poor and comments are lacking.

Charles B. Cameron