tmp1 = (tmp2 == tmp3)

[Pasacco]

------------------------------------------------
wire [1:0] tmp2;
wire [1:0] tmp3;
wire tmp1;
.....
------------------------------------------------

Does the following two sentences have same meaning?

assign tmp1 = (tmp2 == tmp3);
assign tmp1 = (tmp2 == tmp3) ? 1'b1 : 1'b0;

 

[Glen Herrmannsfeldt]

Pasacco wrote:
(snip)

Does the following two sentences have same meaning?

assign tmp1 = (tmp2 == tmp3);
assign tmp1 = (tmp2 == tmp3) ? 1'b1 : 1'b0;

Is the homework due today?

If tmp2 or tmp3 contain x or z then they might be different.

My verilog book isn't here right now, though.
Do you have a book?

-- glen

 

[Explorer]

(tmp2 == tmp3) will return x, if tmp2 or tmp3 contain x's of z's. In
such a case below code you will have x as output when tmp2 or tmp3 are
in non determinate state (outside 1, 0)

assign    tmp1 = (tmp2 == tmp3);

Coming to the second statement, when ternary operator (or conditional
operator) sees x/z in conditional expression, it evaluates both true
and false condition, and merges the result. since your branches are
giving orthogonal result, so ternary operator will merge to give x

assign    tmp1 = (tmp2 == tmp3) ? 1'b1 : 1'b0;

hence as per my understanding both statement will return the same in
all conditions.