timing with verilog

Hi Guys,

I am still learning the many possibilities of verilog and would like
to know if there are some techniques in verilog that would allow me to
do the following:
I have a signal that is pulsing from an external device. This
signal,Signal1, lasts as a high pulse for 10us and stays low for 10us
and repeats itself. I would like to count some other pulse (a faster
pulser than Signal1) based on a time window of 2.5us to 7.5us of the
high from Signal1. In other words, I would like to turn on a counter
at specific times of Signal1. Is there any way I can do this in
verilog ?

Thanks,
Uchenna

 

[Robert Miles]

<uraniumore238@gmail.com> wrote in message
news:54b78e84-d1fb-4da9-adba-32f359a319a0@v39g2000pro.googlegroups.com...

Hi Guys,

I am still learning the many possibilities of verilog and would like
to know if there are some techniques in verilog that would allow me to
do the following:
I have a signal that is pulsing from an external device. This
signal,Signal1, lasts as a high pulse for 10us and stays low for 10us
and repeats itself. I would like to count some other pulse (a faster
pulser than Signal1) based on a time window of 2.5us to 7.5us of the
high from Signal1. In other words, I would like to turn on a counter
at specific times of Signal1. Is there any way I can do this in
verilog ?

Thanks,
Uchenna
..

I haven't seen a way to trigger a signal before the signal that triggers
it. However, you might want to try starting the window 2.5us after
Signal1 rises, then ending it 5.0us later.

 

On Oct 21, 11:10 pm, uraniumore...@gmail.com wrote:

I have a signal that is pulsing from an external device. This
signal,Signal1, lasts as a high pulse for 10us and stays low for 10us
and repeats itself. I would like to count some other pulse (a faster
pulser than Signal1) based on a time window of 2.5us to 7.5us of the
high from Signal1. In other words, I would like to turn on a counter
at specific times of Signal1. Is there any way I can do this in
verilog ?

Do you want to build hardware to do this? Or is it something
that you want to do in a Verilog test bench?

If it's a test bench, Verilog provides very nice facilities
for doing things as a function of time:

`timescale 1ns/1ns
....
reg CounterEnable; // will enable your other counter

always begin
// Wait for Signal1 to go high
@(posedge Signal1);
// Wait for 2.5us:
#2500;
// Enable your counter
CounterEnable = 1;
// Wait for 5us:
#5000;
// Disable the counter:
CounterEnable = 1;
// And then loop around again:
end


But this won't work in hardware, because there is no way
to synthesise the long delays. Instead you need a fast
clock that will count off the appropriate length of time.
Think of what hardware you want to build to achieve this,
and only then worry about describing it in Verilog
--
Jonathan Bromley

 

[mengxipeng@gmail.com]

i try to reslove this issue on my way


module tw_count(clk,rst,en,signal1,fast_pulser,c);
input clk; // the main clock, it is faster than signal1 and
fast_pulser
input rst; // reset
input en; // if en is high, count will work, this signal whill
start at 2.5us , and end at 7.5us, it's controled by external circuit
input signal1; //
input fast_pulser; // the faster pulser than Signal1
output [31:0] c; // the counter output, i don't konw what size fit?
assumpt its size is 32
reg [31:0] c;
reg fast_pulser_d; //


always @(posedge clk)
begin
fast_pulser_d<=fast_pulser;
if(rst)
c<=32'h000000000;
else
if(en && ~fast_pulser_d && fast_pulser &&
signal1 )
// when signal1 is high and en valid and have
a faster pulse, counter will add 1
c<= c + 32'h1;
end
endmodule



hope my code can help




On Oct 22, 8:25 pm, s...@oxfordbromley.plus.com wrote:

On Oct 21, 11:10 pm, uraniumore...@gmail.com wrote:

I have a signal that is pulsing from an external device. This
signal,Signal1, lasts as a high pulse for 10us and stays low for 10us
and repeats itself. I would like to count some other pulse (a faster
pulser than Signal1) based on a time window of 2.5us to 7.5us of the
high from Signal1. In other words, I would like to turn on a counter
at specific times of Signal1. Is there any way I can do this in
verilog ?

Do you want to build hardware to do this? Or is it something
that you want to do in a Verilog test bench?

If it's a test bench, Verilog provides very nice facilities
for doing things as a function of time:

`timescale 1ns/1ns
...
reg CounterEnable; // will enable your other counter

always begin
// Wait for Signal1 to go high
@(posedge Signal1);
// Wait for 2.5us:
#2500;
// Enable your counter
CounterEnable = 1;
// Wait for 5us:
#5000;
// Disable the counter:
CounterEnable = 1;
// And then loop around again:
end

But this won't work in hardware, because there is no way
to synthesise the long delays. Instead you need a fast
clock that will count off the appropriate length of time.
Think of what hardware you want to build to achieve this,
and only then worry about describing it in Verilog
--
Jonathan Bromley