timing simulation problem

[mike]

Hi,

I want that u help me if u can:

I use the XST tool for synthesis and implementation and i choose to
make the RAM whowever when i make the timing simulation with the
modelsim SE ( with sdf file of ram) i never see the data in
output....for this i want that u can say me where is my error....

Thanks for helping me

These are the files:



library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity ram is
generic(DEEP: integer := 4;
WIDTH:integer := 8);
port(wr,clk:std_logic;
adram:in std_logic_vector(DEEP downto 1);
data_in: std_logic_vector (WIDTH downto 1);
data_outut std_logic_vector (WIDTH downto 1));

end ram;

architecture beh_ram of ram is

begin
process_ram: process(clk)
type memory is array (15 downto 0) of std_logic_vector (width
downto 1);
variable mem : memory;
begin
if clk ='1' and clk'event then
data_out <= ( others => '0');
if wr ='1' then
mem(CONV_INTEGER(adram)):=data_in;
else
data_out <=mem(CONV_INTEGER(adram));
end if;
end if;
end process;
end;



Its testbench

-- VHDL Test Bench Created from source file ram.vhd -- 15:25:15
07/10/2005
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use IEEE.STD_LOGIC_SIGNED.ALL;
use ieee.STD_LOGIC_TEXTIO.all;
use STD.TEXTIO.all;

ENTITY ram_tb IS
END ram_tb;

ARCHITECTURE beh OF ram_tb IS

COMPONENT ram
generic(DEEP: integer := 4;
WIDTH:integer := 8);
PORT(
wr : IN std_logic;
clk : IN std_logic;
adram : IN std_logic_vector(4 downto 1);
data_in : IN std_logic_vector(8 downto 1);
data_out : OUT std_logic_vector(8 downto 1)
);
END COMPONENT;

SIGNAL wr : std_logic;
SIGNAL clk : std_logic:='0';
SIGNAL adram : std_logic_vector(4 downto 1);
SIGNAL data_in : std_logic_vector(8 downto 1);
SIGNAL data_out : std_logic_vector(8 downto 1);

BEGIN



wr <='1' after 9 ns,'0' after 69 ns;

clk <= not clk after 10 ns;


adram <= "0000" after 9 ns,"0001" after 29 ns,"0010" after 49 ns,
"0000" after 69 ns,
"0001" after 89 ns,"0010" after 109 ns;

data_in <= "00000001" after 9 ns,"00000010" after 29 ns,"00000011"
after 49 ns;

test_design: ram generic map(deep => 4,
width => 8)
PORT MAP(
wr => wr,
clk => clk,
adram => adram,
data_in => data_in,
data_out => data_out
);

END;

 

I think your case's same that I ever found. Main problem is in
testbench file.
I change clk signal assignment that is assigned at 0 ns to assigned a
delay
from 0 ns such as 1 ns. I think something in library module want to
setup
at time 0 ns.

-- old code ------------------
clk <= not clk after 10 ns;
-- old code ------------------

-- new code ------------------
process
begin
if clk='1' then
clk <= '0';
elsif clk='0' then
clk <= '1';
else
clk <= '0' after 1 ns;
end if;
wait for 10 ns;
end process;
-- new code ------------------

 

[Andy Peters]

mike wrote:

Hi,

I want that u help me if u can:

I use the XST tool for synthesis and implementation and i choose to
make the RAM whowever when i make the timing simulation with the
modelsim SE ( with sdf file of ram) i never see the data in
output....for this i want that u can say me where is my error....

Thanks for helping me

These are the files:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

[Again with the STD_LOGIC_ARITH. Xilinx: fix your templates!]

Its testbench

-- VHDL Test Bench Created from source file ram.vhd -- 15:25:15
07/10/2005
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use IEEE.STD_LOGIC_SIGNED.ALL;
use ieee.STD_LOGIC_TEXTIO.all;
use STD.TEXTIO.all;

ENTITY ram_tb IS
END ram_tb;

ARCHITECTURE beh OF ram_tb IS

COMPONENT ram
generic(DEEP: integer := 4;
WIDTH:integer := 8);
PORT(
wr : IN std_logic;
clk : IN std_logic;
adram : IN std_logic_vector(4 downto 1);
data_in : IN std_logic_vector(8 downto 1);
data_out : OUT std_logic_vector(8 downto 1)
);
END COMPONENT;

SIGNAL wr : std_logic;
SIGNAL clk : std_logic:='0';
SIGNAL adram : std_logic_vector(4 downto 1);
SIGNAL data_in : std_logic_vector(8 downto 1);
SIGNAL data_out : std_logic_vector(8 downto 1);

BEGIN

clk <= not clk after 10 ns;

Ummm...did you bother looking at this in the waveform viewer? Didn't
the clk signal show up in red, and its value set to 'X' or 'U' ??

See, you didn't bother to initialize clk before assigning anything to
it.

-a