Timing Simulation in Active HDL

[ashwin]

hello everyone,
Could anyone tell me,
the steps needed to perform for timing simulation in Aldec Active HDL.

thanks
ashwin

 

The easiest way to find such information is to use Aldec's support
website:

http://support.aldec.com

Type in timing simualtion and you will find manuals and appnotes
regarding timing simulation. Some app notes are specially for certain
vendor such as Xilinx or Altera.

Another good source if you are new with Active-HDL is to view demo
movies:

http://www.aldec.com/products/active-hdl/multimediademo/

There is one specially made for "timing simulation". It is a movie with
both written and audio instructions so it should get you started very
quickly.

 

ashwin wrote:

hello everyone,
Could anyone tell me,
the steps needed to perform for timing simulation in Aldec Active HDL.

thanks
ashwin

I totally agree with the first answer to your post. Aldec help is
excellent and their demos are very good. The main difference between
the timing and functional simulation is that the VHDL source code for
the timing simulation is a file produced by your synthesis tool. This
file contains the timing information for the device you chose based on
the device architecture and your VHDL source code.

Charles