L
L. Coleman
Guest
Hello all.
I am working on a microcontroller design using the Cadence tools and an
OKI 0.16 standard cell library. I optimized my design for speed as much
as possible before layout using the Synopsys synthesizer to analyze the
critical path. The Synopsys and PrimeTime tools estimated the design
would run at a maximum clock rate of 250MHz. I then used SOC Encounter
to create a layout. After creating a floorplan, running place, trial
route, and optimize in Encounter I ran a timing analysis. The timing
analysis indicates that the design will run at a maximum clock rate of
180MHz (much slower than the Synopsys estimate). Is that much of a
difference between pre-layout and post-layout timing expected? Can
anyone suggest a way to get the final layout to perform more closely to
the Synopsys estimate?
Thanks.
Laura
I am working on a microcontroller design using the Cadence tools and an
OKI 0.16 standard cell library. I optimized my design for speed as much
as possible before layout using the Synopsys synthesizer to analyze the
critical path. The Synopsys and PrimeTime tools estimated the design
would run at a maximum clock rate of 250MHz. I then used SOC Encounter
to create a layout. After creating a floorplan, running place, trial
route, and optimize in Encounter I ran a timing analysis. The timing
analysis indicates that the design will run at a maximum clock rate of
180MHz (much slower than the Synopsys estimate). Is that much of a
difference between pre-layout and post-layout timing expected? Can
anyone suggest a way to get the final layout to perform more closely to
the Synopsys estimate?
Thanks.
Laura