timing module for 50Khz signal using spartan 3an

Guest
Hi All,

I am trying to develop a timer module. Think of this timer module as a
black box that takes in a 50Khz signal output a window signal and a
period signal. My problem is I want to reset the countera, period and
window when there is a pulse on the Reference signal .. This code
gives me an error. I am trying to fix my code, can somebody help me
with this puzzle ...

Here is my code:
MasterCLK is 10Mhz input ...
Reference is 50Khz input
module timer( MasterCLK, Reference, period, Reset, Window
);

input MasterCLK;
input Reference;
output reg Window;
output reg period;
output reg RightReference;
input Reset;
reg Refout;
reg MCLK;
reg [31:0] countera;
reg Qreset;

always @ (posedge MasterCLK)
begin

Refout<=Reference; //
countera<=countera+1'b1; //increment the counter
//reset countera and period when Refout is asserted

case(countera)
01: period <= 1; //set cycle (up-count)
16: Window <= 1; //set pulse window
81: Window <= 0; //reset pulse window
100: period <= 0; //set cycle (down-count)
101: countera <= 0;
endcase
end

always @ (posedge Refout)
begin
countera <= 0; //reset counter
period <= 0; //reset period flip-flop
Window <= 0;
end

endmodule
 
What error message on what tool?

>On Jan 28, 8:59 pm, uraniumore...@gmail.com wrote stuff...
 
On Wed, 28 Jan 2009 20:59:29 -0800 (PST), uraniumore238@gmail.com
wrote:

Hi All,

I am trying to develop a timer module. Think of this timer module as a
black box that takes in a 50Khz signal output a window signal and a
period signal. My problem is I want to reset the countera, period and
window when there is a pulse on the Reference signal .. This code
gives me an error. I am trying to fix my code, can somebody help me
with this puzzle ...
Click to expand...
You have two major issues with your code:

Here is my code:
MasterCLK is 10Mhz input ...
Reference is 50Khz input
module timer( MasterCLK, Reference, period, Reset, Window
);

input MasterCLK;
input Reference;
output reg Window;
output reg period;
output reg RightReference;
This port is missing from the module port list. This should give you a
Click to expand...
compilation error in simulation.
input Reset;
reg Refout;
reg MCLK;
reg [31:0] countera;
reg Qreset;

always @ (posedge MasterCLK)
begin

Refout<=Reference; //
countera<=countera+1'b1; //increment the counter
//reset countera and period when Refout is asserted

case(countera)
01: period <= 1; //set cycle (up-count)
16: Window <= 1; //set pulse window
81: Window <= 0; //reset pulse window
100: period <= 0; //set cycle (down-count)
101: countera <= 0;
endcase
end

always @ (posedge Refout)
begin
countera <= 0; //reset counter
Click to expand...
You're assigning countera in two different always blocks which is not
a synthesizable construct. You need to merge all register assignments
in a single always block.

period <= 0; //reset period flip-flop
Window <= 0;
end

endmodule
--
Click to expand...
Muzaffer Kal

DSPIA INC.
ASIC/FPGA Design Services
http://www.dspia.com
 
On Jan 29, 9:27 am, SysTom <tjo...@echelon.com> wrote:
What error message on what tool?



On Jan 28, 8:59 pm, uraniumore...@gmail.com wrote stuff...- Hide quoted text -

- Show quoted text -
Click to expand...
Multi-source error on Xilinx - ISE 10.1
 
On Jan 29, 10:53 am, uraniumore...@gmail.com wrote:
On Jan 29, 9:27 am, SysTom <tjo...@echelon.com> wrote:

What error message on what tool?

On Jan 28, 8:59 pm, uraniumore...@gmail.com wrote stuff...- Hide quoted text -

- Show quoted text -

Multi-source error on Xilinx - ISE 10.1
Click to expand...
Hi Guys,

I did some reconstruction to my code and came up the with follow. Now
my problem is when I run the simulation. (problem) I see a the window
signal produce a logic one, within the high period, but I cannot see
one within the low period Then alternate. Somewhere in my code I have
an error, and I have been debugging for some time and cannnot find the
error. Please help by running the simulation and please explain to me
when I have done wrong ?
 
On Jan 29, 4:49 pm, uraniumore...@gmail.com wrote:
On Jan 29, 10:53 am, uraniumore...@gmail.com wrote:

On Jan 29, 9:27 am, SysTom <tjo...@echelon.com> wrote:

What error message on what tool?

On Jan 28, 8:59 pm, uraniumore...@gmail.com wrote stuff...- Hide quoted text -

- Show quoted text -

Multi-source error on Xilinx - ISE 10.1

Hi Guys,

I did some reconstruction to my code and came up the with follow. Now
my problem is when I run the simulation. (problem) I see a the window
signal produce a logic one, within the high period, but I cannot see
one within the low period Then alternate. Somewhere in my code I have
an error, and I have been debugging for some time and cannnot find the
error. Please help by running the simulation and please explain to me
when I have done wrong ?
Click to expand...
`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 19:51:03 01/28/2009
// Design Name: timer
// Module Name: C:/XilProjects/4bitCountN/countera/timer_tb.v
// Project Name: countera
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: timer
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////

module timer_tb;

// Inputs
reg MasterCLK;
reg Reference;
reg Reset;

// Outputs
wire period;
wire RightReference;
wire Window;

// Instantiate the Unit Under Test (UUT)
timer uut (
.MasterCLK(MasterCLK),
.Reference(Reference),
.period(period),
.Reset(Reset),
.Window(Window)
);

initial begin
// Initialize Inputs
MasterCLK = 0;
Reference = 0;
Reset = 0;

// Wait 100 ns for global reset to finish
#100;
Reset = 1;
#10;
Reset = 0;
// Add stimulus here

end

always #100 MasterCLK = ~MasterCLK; //10Mhz clock signal
always #20000 Reference = ~Reference; //50Khz reference signal


endmodule

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 18:47:19 01/27/2009
// Design Name:
// Module Name: timer
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
/*module timer( MasterCLK, Reference, period, Reset, Window
);

input MasterCLK;
input Reference;
output reg Window;
output reg period;
input Reset;
reg QReset;
reg Refout;
reg [31:0] countera;
reg trigger;

always @ (posedge Refout or posedge QReset)
begin
if(QReset)
trigger <= 0;
else
trigger <=1; //edge of the reference pulse detected
end

always @ (posedge MasterCLK)
begin

Refout<=Reference; //

QReset <= Reset;

if(QReset) //manual reset
begin
period <= 0;
Window <= 0;
countera <=0;
end


countera<=countera+1'b1; //increment the counter
//reset countera and period when Refout is asserted

if(Refout & trigger) //reset the counter, low the period and window at
the reference pulse
begin
countera <= 0;
period <= 0;
Window <= 0;
end

if(Refout)
begin
case(countera)
0: period <= 1; //set cycle (up-count)
15: Window <= 1; //set pulse window
80: begin Window <= 0; end //reset pulse window
99: begin period <= 0; //set cycle (down-count)
QReset <= 1; end
100: countera <= 0;
endcase
end

if(Window == 0 & trigger == 1)
QReset <= 1;

end


endmodule
*/
module timer( MasterCLK, Reference, period, Reset, Window
);


input MasterCLK;
input Reference;
output reg Window;
output reg period;
input Reset;
reg Refout;
reg MCLK;
reg [31:0] countera;
reg QReset;
reg triggerpos;
reg triggerneg;


always @ (posedge MasterCLK)
begin


Refout<=Reference; //
QReset<= Reset;
countera<=countera+1'b1; //increment the counter
//reset countera and period when Refout is asserted

case(countera)
01: period <= 1; //set cycle (up-count)
16: Window <= 1; //set pulse window
81: Window <= 0; //reset pulse window
100: period <= 0; //set cycle (down-count)
101: countera <= 0; //
endcase


if(Refout & triggerneg)
begin
countera <= 0; //reset counter
period <= 0; //reset period flip-flop
Window <= 0;
QReset<= 0;
end

end
//problem is here
always @ (posedge Refout or posedge QReset)
begin
if(QReset)
triggerpos <= 0;
else
triggerpos <= 1;
end

always @ (negedge Refout or posedge QReset)
begin
if(QReset)
triggerneg <= 0;
else
triggerneg <= 1;
end

endmodule
 
On Thu, 29 Jan 2009 16:50:22 -0800 (PST), wrote:

module timer( MasterCLK, Reference, period, Reset, Window);
Click to expand...
I haven't run the sim but you are really, really on the
wrong track - you need to start thinking all over again.

Using the asynchronous reset input of a FF as an edge
detector is disgusting and will cause much trouble in
the real world. Just don't do it.

I went back to your original code in an attempt to
understand what you're trying to do. In that code,
the problem that prevented compilation was the fact
that you have assigned to Window from two different
"always" blocks; that's legal Verilog, but it cannot
be synthesised. But the problem runs much deeper
than that. One process is triggered by
posedge(Refout)
but Refout is a SYNCHRONOUS signal, generated in
the process clocked by MasterCLK! So it would be
far more sensible to roll the posedge(Refout) logic
into the MasterCLK process.

always @ (posedge MasterCLK)
begin
Refout<=Reference;

This creates a new version of Reference that's synchronised to
MasterCLK. So let's edge-detect that SYNCHRONOUSLY instead
of using posedge to do it; then we can put all the logic
into one process. Here we go... Oh, and by the way,
narrative comments in the code are good... very good...
Have you any idea how much it raises my blood pressure to
see comments like this....

countera<=countera+1'b1; //increment the counter

YES, YES, I was not born yesterday, I can see that you're
incrementing "countera" on that line of code. For pity's
sake, tell me WHY you're doing it!


always @ (posedge MasterCLK or posedge Reset)

if (Reset) begin

// Zap everything on power-up reset
RefSync <= 0;
RefSyncDelayed <= 0;
countera <= 0;
period <= 0;
Window <= 0;

end else begin

// Resynchronize Reference, and create a
// delayed version so we can edge-detect it.
RefSync<=Reference;
RefSyncDelayed <= RefSync;

// Manage the counter. Normally it counts
// in the sequence 0,1,....100,101,0,1...
// but as we'll see later this count may be
// aborted by a rising edge on Reference.
//
if (countera == 101)
countera <= 0;
else
countera<=countera+1'b1;

// Generate Window and Period outputs as a function
// of counter; but, like the counter, they may be reset
// by a rising edge on Reference - see later.
//
case (countera)
1: period <= 1;
16: Window <= 1;
81: Window <= 0; // timeout on Window
100: period <= 0; // timeout on period
endcase

// When Reference rises, most of this behaviour is
// overridden and the whole thing is reset.
//
if (RefSync & !RefSyncDelayed) // rising edge
begin
countera <= 0; //reset counter
period <= 0; //reset period flip-flop
Window <= 0;
end

end // clocked always block

I still don't understand what the code is trying to do,
but at least this should compile cleanly both for simulation
and for synthesis. Of course, you need to declare all the
regs I added.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
 
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