Timing doubt...

[Element Blue]

Hi All,
I am in considerable doubt over the behaviour of the following
statements:
module test2();
reg a,b,c;
initial
begin
a=0;
#10 a=1;
#20 a=0;
end
always
begin
b=#15 (~a);
#15 c=(~a);
end
endmodule

What is the difference between the 2 statements in the always block ? I
did a simulation, and indeed the signals b and c had different shapes.
What is the principle of these assignments?
Thanks a lot,
EB.

 

[Ajeetha Kumari]

Hi,
Please refer a decent book on verilog, else search previous postings
of this group.

HTH,
Ajeetha



Element Blue <supreet@wrongdomain.com> wrote in message news:<Pine.LNX.4.61.0411191807290.30517@phenix.rootshell.be>...

Hi All,
I am in considerable doubt over the behaviour of the following
statements:
module test2();
reg a,b,c;
initial
begin
a=0;
#10 a=1;
#20 a=0;
end
always
begin
b=#15 (~a);
#15 c=(~a);
end
endmodule

What is the difference between the 2 statements in the always block ? I
did a simulation, and indeed the signals b and c had different shapes.
What is the principle of these assignments?
Thanks a lot,
EB.

 

[Neo]

always
begin
b=#15 (~a);
#15 c=(~a);
end
endmodule

What is the difference between the 2 statements in the always block ? I
did a simulation, and indeed the signals b and c had different shapes.
What is the principle of these assignments?
Thanks a lot,
EB.

The second one evaluates ~a after #15 and assigns to b
the first one evaluates ~a immediately but assigns after #15

Neo