Timing Diagram to HDL Translation

  • Thread starter Kieran Francisco
  • Start date
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Kieran Francisco

Guest
Hello,

I am looking for a Tool that I can generate VHDL and/or Verilog
directly from a timing diagram. I have a bus system in my design that
is common to many IP blocks and its currently specified as a series of
read and write bus cycles. I would like to enter these bus cycle
timings and generate HDL directly from them. Anyone have any good
ideas.

Thanks, Kieran.
 
In article <e50b1b3b.0309080617.2919f96c@posting.google.com>,
Kieran Francisco <kieranfrancisco@yahoo.com> wrote:
Hello,

I am looking for a Tool that I can generate VHDL and/or Verilog
directly from a timing diagram. I have a bus system in my design that
is common to many IP blocks and its currently specified as a series of
read and write bus cycles. I would like to enter these bus cycle
timings and generate HDL directly from them. Anyone have any good
ideas.

Thanks, Kieran.
Click to expand...

Interesting idea. So, if I understand correctly, you would want to
generate a state machine from a timing diagram and then generate an HDL
of the state machine. Is that what you're proposing?

Phil
 
Take a look at http://www.timingdesigner.com/timingdesigner.asp .

Jim Wu
jimwu88NOOOSPAM@yahoo.com
http://www.geocities.com/jimwu88/chips


"Kieran Francisco" <kieranfrancisco@yahoo.com> wrote in message
news:e50b1b3b.0309080617.2919f96c@posting.google.com...
Hello,

I am looking for a Tool that I can generate VHDL and/or Verilog
directly from a timing diagram. I have a bus system in my design that
is common to many IP blocks and its currently specified as a series of
read and write bus cycles. I would like to enter these bus cycle
timings and generate HDL directly from them. Anyone have any good
ideas.

Thanks, Kieran.
Click to expand...
 
Kieran,

I don't believe timing diagrams can completely specify bus interface.
They may define some functional constraints, but this will be only
partial design specification (I even dont mention missed specification
for "backdoor" side of bus interface). However, partial specification
still may be useful for automatic generation of verification
constraints in OVL, OVA, Specman or PSL(Sugar) format. For this
purpose, you may try TestBencher Pro from SynaptiCAD (If you'll decide
to evaluate this tool, it would be interesting to get your comments
about it).

Regards,
Alexander Gnusin
www.TCLforEDA.net
 
Our WaveFormer Pro and TestBencher Pro products both have the capability
to do this to varying degrees. You can find out more at our web site:

http://www.syncad.com

best regards,

Dan Notestein
SynaptiCAD

kieranfrancisco@yahoo.com (Kieran Francisco) wrote in
news:e50b1b3b.0309080617.2919f96c@posting.google.com:

Hello,

I am looking for a Tool that I can generate VHDL and/or Verilog
directly from a timing diagram. I have a bus system in my design that
is common to many IP blocks and its currently specified as a series of
read and write bus cycles. I would like to enter these bus cycle
timings and generate HDL directly from them. Anyone have any good
ideas.

Thanks, Kieran.
Click to expand...
 
Dan Notestein <dan@syncad.com> wrote in message news:<Xns93F1E20AE3021dansyncadcom@63.223.5.101>...
Our WaveFormer Pro and TestBencher Pro products both have the capability
to do this to varying degrees. You can find out more at our web site:

http://www.syncad.com

best regards,

Dan Notestein
SynaptiCAD

kieranfrancisco@yahoo.com (Kieran Francisco) wrote in
news:e50b1b3b.0309080617.2919f96c@posting.google.com:

Hello,

I am looking for a Tool that I can generate VHDL and/or Verilog
directly from a timing diagram. I have a bus system in my design that
is common to many IP blocks and its currently specified as a series of
read and write bus cycles. I would like to enter these bus cycle
timings and generate HDL directly from them. Anyone have any good
ideas.

Thanks, Kieran.
Click to expand...
Hi Kieran,

you can try our products - TimingTool or TimingTool Lite.

The TimingTool Lite is our free to use online java applet which allows
users to enter and edit timing diagrams. There are also translators
that supply full VHDL and Verilog outputs from the timing diagrams.

The full product, TimingTool has many more features that may be useful
to you if you are connecting many IP blocks together. This is supplied
as a download which is installed on your local machine (unlike
TimingTool Lite). Some of the extra features include relationships
between edges, parameter tables, a macro language, and excellent
export capabilities (eg. straight to HTML). Also VHDL and Verilog
exports are supplied as with the TimingTool Lite product.

TimingTool can be found at: www.timingtool.com

Hope this helps,

Paul.
 
Dan Notestein <dan@syncad.com> wrote in message news:<Xns93F1E20AE3021dansyncadcom@63.223.5.101>...
Our WaveFormer Pro and TestBencher Pro products both have the capability
to do this to varying degrees. You can find out more at our web site:

http://www.syncad.com

best regards,

Dan Notestein
SynaptiCAD

kieranfrancisco@yahoo.com (Kieran Francisco) wrote in
news:e50b1b3b.0309080617.2919f96c@posting.google.com:

Hello,

I am looking for a Tool that I can generate VHDL and/or Verilog
directly from a timing diagram. I have a bus system in my design that
is common to many IP blocks and its currently specified as a series of
read and write bus cycles. I would like to enter these bus cycle
timings and generate HDL directly from them. Anyone have any good
ideas.

Thanks, Kieran.
Click to expand...

Thank you for all your replies to my posting.

I will try out your recommendations and let you know how I get on.

Kieran
 
I am looking for a Tool that I can generate VHDL and/or Verilog
directly from a timing diagram. I have a bus system in my design that
is common to many IP blocks and its currently specified as a series of
read and write bus cycles. I would like to enter these bus cycle
timings and generate HDL directly from them. Anyone have any good
ideas.
Click to expand...
I am questioning the whole premise on the need to generate HDL from
a timing diagram for TB designs. I personally prefer"
1. A transaction-based approach (see my site under models, veriflang.pdf
Document: Transaction-Based Verification in HDL) where the transator (or
client) makes high level transaction requests, and the server provides the
low-levl interfaces to the DUT. It is not difficult to code a server to do
READs, WRITEs, DMA, IDLE, etc. classes of cyles. If that is difficult, then
you don't understand the design.

2. I also encourge the use of PSL to perform white-box verification for
simulation or formal verification.

----------------------------------------------------------------------------
Ben Cohen Publisher, Trainer, Consultant (310) 721-4830
http://www.vhdlcohen.com/ vhdlcohen@aol.com
Author of following textbooks:
* Using PSL/SUGAR with Verilog and VHDL
Guide to Property Specification Language for ABV, 2003 isbn 0-9705394-4-4
* Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn
0-9705394-2-8
* Component Design by Example ", 2001 isbn 0-9705394-0-1
* VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn 0-7923-8474-1
* VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn 0-7923-8115
------------------------------------------------------------------------------
 
A transaction based approach and a timing diagram based approach are not
mutually exclusive, in fact TestBencher is based on using these two
principles together. The user creates a set of timing diagrams for each
type of transaction supported by a bus functional model and TestBencher
generates a transactor for each timing diagram plus all the upper level
infrastructure for doing things such as triggering the transactions,
randomly generating the transactions and their input parameters, validating
the outputs of the transaction against a golden reference model, etc. The
timing diagrams are significantly easier to create and maintain than hand
coded modules and are much simpler to understand in terms of functionality.
The knowledge of how to implement in HDL code some of the tricker things
you often want to do in a transaction is embedded into the tools, so you
just say what you want at a high level and TestBencher generates the
appropriate code.

vhdlcohen@aol.com (VhdlCohen) wrote in
news:20030910202356.19586.00000518@mb-m20.aol.com:

I am questioning the whole premise on the need to generate HDL from
a timing diagram for TB designs. I personally prefer"
1. A transaction-based approach (see my site under models,
veriflang.pdf Document: Transaction-Based Verification in HDL) where
the transator (or client) makes high level transaction requests, and
the server provides the low-levl interfaces to the DUT. It is not
difficult to code a server to do READs, WRITEs, DMA, IDLE, etc.
classes of cyles. If that is difficult, then you don't understand the
design.
Click to expand...
 
You didn't mention if you needed a free tool....if not, an excellent tool
for doing this is Quickbench from Forte Design Systems. It's easy to use and
very powerful (you can do things like pause a timing diagram, parameterize
it, etc.).

Being primarily a hardware designer, timing diagrams are a common form of
thinking/explaining for me. I used this in my last job to do verification of
some IP we were developing for a customer and it was the best verification
environment I have used.


"Kieran Francisco" <kieranfrancisco@yahoo.com> wrote in message
news:e50b1b3b.0309080617.2919f96c@posting.google.com...
Hello,

I am looking for a Tool that I can generate VHDL and/or Verilog
directly from a timing diagram. I have a bus system in my design that
is common to many IP blocks and its currently specified as a series of
read and write bus cycles. I would like to enter these bus cycle
timings and generate HDL directly from them. Anyone have any good
ideas.

Thanks, Kieran.
Click to expand...
 
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